公开(公告)号：US06859413B2

公开(公告)日：2005-02-22

申请号：US10260087

申请日：2002-09-27

申请人： John T. Phan ,  Michael Armand Roberge

发明人： John T. Phan ,  Michael Armand Roberge

IPC分类号： G11C7/22 ,  G11C11/4076 ,  G11C8/00

CPC分类号： G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076

摘要： Disclosed herein are a method and structure, in an integrated circuit having at least one delay locked loop circuit (DLL), for determining a Lock Latency value of a DLL output clock signal. The disclosed method includes temporarily disabling a first clock signal in response to the DLL doing at least one of approaching and acquiring lock; and then thereafter determining a Lock Latency value in response to examining a DLL output clock signal generated in response to the first clock signal.

摘要翻译： 这里公开了一种在具有至少一个延迟锁定环电路（DLL）的集成电路中用于确定DLL输出时钟信号的锁定延迟值的方法和结构。 所公开的方法包括响应于DLL进行接近和获取锁中的至少一个而临时禁用第一时钟信号; 然后响应于检查响应于第一时钟信号而产生的DLL输出时钟信号来确定锁定延迟值。