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1.发明授权Systems and methods for maximizing breakdown voltage in semiconductor devices 有权用于最大化半导体器件中的击穿电压的系统和方法公开(公告)号：US08110494B1
公开(公告)日：2012-02-07
申请号：US12549196
申请日：2009-08-27
IPC分类号： H01L21/4763
CPC分类号： H01L21/76885 , H01L29/0619 , H01L29/0623 , H01L29/1608 , H01L29/2003 , H01L29/66416
摘要： Systems and methods for maximizing the breakdown voltage of a semiconductor device are described. In a multiple floating guard ring design, the spacing between two consecutive sets of floating guard rings may increase with their distance from the main junction while maintaining depletion region overlap, thereby alleviating crowding and optimally spreading the electric field leading to a breakdown voltage that is close to the intrinsic material limit. In another exemplary embodiment, fabrication of floating guard rings simultaneously with the formation of another semiconductor feature allows precise positioning of the first floating guard ring with respect to the edge of a main junction, as well as precise control of floating guard ring widths and spacings. In yet another exemplary embodiment, design of the vertical separation between doped regions of a semiconductor device adjusts the device's gate-to-source breakdown voltage without affecting the device's pinch-off voltage.
摘要翻译： 描述了用于最大化半导体器件的击穿电压的系统和方法。 在多重浮动保护环设计中，两个连续组的浮动保护环之间的间隔可以随其与主结的距离而增加，同时保持耗尽区重叠，从而减轻拥挤并最佳地扩展电场，导致击穿电压接近 到本质限制。 在另一个示例性实施例中，与形成另一半导体特征同时制造浮动保护环允许第一浮动保护环相对于主结的边缘精确定位，以及漂浮保护环宽度和间隔的精确控制。 在另一示例性实施例中，半导体器件的掺杂区域之间的垂直间隔的设计调节器件的栅极至源极击穿电压，而不会影响器件的截止电压。
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2.发明授权Systems and methods for maximizing breakdown voltage in semiconductor devices 有权用于最大化半导体器件中的击穿电压的系统和方法公开(公告)号：US07667242B1
公开(公告)日：2010-02-23
申请号：US11601064
申请日：2006-11-17
IPC分类号： H01L29/74
CPC分类号： H01L21/76885 , H01L29/0619 , H01L29/0623 , H01L29/1608 , H01L29/2003 , H01L29/66416
摘要： Systems and methods for maximizing the breakdown voltage of a semiconductor device are described. In a multiple floating guard ring design, the spacing between two consecutive sets of floating guard rings may increase with their distance from the main junction while maintaining depletion region overlap, thereby alleviating crowding and optimally spreading the electric field leading to a breakdown voltage that is close to the intrinsic material limit. In another exemplary embodiment, fabrication of floating guard rings simultaneously with the formation of another semiconductor feature allows precise positioning of the first floating guard ring with respect to the edge of a main junction, as well as precise control of floating guard ring widths and spacings. In yet another exemplary embodiment, design of the vertical separation between doped regions of a semiconductor device adjusts the device's gate-to-source breakdown voltage without affecting the device's pinch-off voltage.
摘要翻译： 描述了用于最大化半导体器件的击穿电压的系统和方法。 在多重浮动保护环设计中，两个连续组的浮动保护环之间的间隔可以随其与主结的距离而增加，同时保持耗尽区重叠，从而减轻拥挤并最佳地扩展电场，导致击穿电压接近 到本质限制。 在另一个示例性实施例中，与形成另一半导体特征同时制造浮动保护环允许第一浮动保护环相对于主结的边缘精确定位，以及漂浮保护环宽度和间隔的精确控制。 在另一示例性实施例中，半导体器件的掺杂区域之间的垂直间隔的设计调节器件的栅极至源极击穿电压，而不会影响器件的截止电压。
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