公开(公告)号：US20050094729A1

公开(公告)日：2005-05-05

申请号：US10913574

申请日：2004-08-06

申请人： John Yuan ,  Steven Smith ,  Srikrishna Ramaswamy ,  Zheng Luo

发明人： John Yuan ,  Steven Smith ,  Srikrishna Ramaswamy ,  Zheng Luo

IPC分类号： H04N7/12 ,  H04N7/26 ,  H04N7/50

CPC分类号： H04N19/42 ,  H04N19/61

摘要： A system, method, and computer readable medium adapted to provide software and hardware partitioning for multi-standard video compression and decompression comprises a master-slave bus, a peer-to-peer bus, and an inter-processor communications bus, a prediction engine, a filter engine, and a transform engine, and a video encode control processor, and a video decode control processor adapted to utilize the master-slave bus to interact with the video hardware engines for control flow processing, the peer-to-peer bus for data flow processing, and the inter-processor communications bus for inter-processor communications, and a system data bus adapted to permit data exchange between system resources, the busses, the engines, and the processors.

摘要翻译： 适于提供用于多标准视频压缩和解压缩的软件和硬件分区的系统，方法和计算机可读介质包括主 - 从总线，对等总线和处理器间通信总线，预测引擎 ，滤波器引擎和变换引擎，以及视频编码控制处理器，以及视频解码控制处理器，其适于利用主从总线与视频硬件引擎进行交互以进行控制流处理，对等总线 用于数据流处理，以及用于处理器间通信的处理器间通信总线，以及适于允许系统资源，总线，引擎和处理器之间的数据交换的系统数据总线。

公开(公告)号：US20080170611A1

公开(公告)日：2008-07-17

申请号：US11878212

申请日：2007-07-23

申请人： Srikrishna Ramaswamy

发明人： Srikrishna Ramaswamy

IPC分类号： H04B1/66

CPC分类号： H04N19/436 ,  H04N19/42 ,  H04N19/61

摘要： A configurable functional multi-processing architecture for video processing. The architecture may be utilized as integrated circuit devices for video compression based on multi-processing at a functional level. The architecture may also provide a function based multi-processing system for video compression and decompression and systems and methods for development of integrated circuit devices for video compression based on multi-processing at a functional level. A function based multi-processing system for video compression and decompression includes one or more functional elements, a high performance video pipeline, a video memory management unit, one or more busses for communication, and a system bus for communication between higher level system resources, functional elements, video pipeline, and video memory management unit. Each functional element selectively includes one or more customized processor elements, one or more hardwired accelerator elements or one or more customized processor elements and hardwired accelerator elements.

摘要翻译： 用于视频处理的可配置功能多处理架构。 该架构可以用作基于功能级别的多处理的用于视频压缩的集成电路装置。 该架构还可以提供用于视频压缩和解压缩的基于功能的多处理系统，以及用于基于功能级别的多处理来开发用于视频压缩的集成电路设备的系统和方法。 用于视频压缩和解压缩的基于功能的多处理系统包括一个或多个功能元件，高性能视频流水线，视频存储器管理单元，用于通信的一个或多个总线，以及用于在较高级系统资源之间进行通信的系统总线， 功能元件，视频管线和视频存储器管理单元。 每个功能元件选择性地包括一个或多个定制的处理器元件，一个或多个硬连线加速器元件或一个或多个定制的处理器元件和硬连线加速器元件。