公开(公告)号：US11002760B1

公开(公告)日：2021-05-11

申请号：US15889623

申请日：2018-02-06

申请人： Johnstech International Corporation

发明人： Jeffrey Sherry ,  Dennis Wagner

IPC分类号： G01R1/04 ,  G01R3/00 ,  G01R31/28

摘要： A system and method for reducing inductance and capacitance and shielding signals in an integrated circuit test for devices under test (DUT) is disclosed. Inductance and capacitance are reduced in two ways. First, by recessing the contact pin housing 22 directly into the load board 20 thereby eliminating much of distance between the load board and DUT. Second, surrounding the slot/well 50 in which each RF contact pin resides in the housing with a ground isolation cage 46,46a, 48, 47 of electrically conductive strips or rings at the top and bottom of the housing adjacent the slot with connecting vias thereby creating an isolation cage against RF cross talk transmission and further lowering inductance and capacitance.