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公开(公告)号：US09141255B2
公开(公告)日：2015-09-22
申请号：US12974346
申请日：2010-12-21
申请人： Jeffrey D. Stroomer , Jonathan B. Ballagh , Roger B. Milne , Jeffrey C. Ward , Krista M. Marks , Thomas E. Fischaber
发明人： Jeffrey D. Stroomer , Jonathan B. Ballagh , Roger B. Milne , Jeffrey C. Ward , Krista M. Marks , Thomas E. Fischaber
IPC分类号： G06F3/00 , G06F5/00 , G06F3/0481
CPC分类号： G06F3/0481
摘要： Techniques for creating a mosaic using user-created content on a content sharing site. Embodiments of the invention may provide an interface on the content sharing site to allow users to create content. Embodiments may then determine a suitability value between the user-created content and portions of a mosaic, and insert the user-created content into a particular portion of the mosaic based on the determined suitability value for the particular portion.
摘要翻译： 在内容共享网站上使用用户创建的内容创建马赛克的技术。 本发明的实施例可以提供内容共享站点上的接口，以允许用户创建内容。 实施例然后可以确定用户创建的内容和马赛克的部分之间的适合性值，并且基于所确定的特定部分的适用性值将用户创建的内容插入到马赛克的特定部分中。
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公开(公告)号：US07797677B1
公开(公告)日：2010-09-14
申请号：US11268801
申请日：2005-11-08
IPC分类号： G06F9/44
CPC分类号： G06F9/543 , G06F9/541 , G06F17/5054
摘要： A method of passing data among modules of a heterogeneous software system can include identifying a scripted function to be executed within the heterogeneous software system and building a wrapper script by embedding a call to the scripted function and an XTable object associated with the scripted function within the wrapper script. The method further can include executing the wrapper script thereby causing the scripted function to execute and receiving a result from execution of the scripted function.
摘要翻译： 在异构软件系统的模块之间传递数据的方法可以包括识别要在异构软件系统内执行的脚本化功能，以及通过嵌入对脚本化功能的调用和与脚本化功能相关联的XTable对象来构建包装器脚本 包装脚本 该方法还可以包括执行包装器脚本，从而使脚本化功能执行并从脚本化功能的执行接收结果。
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3.发明授权Specification of the hierarchy, connectivity, and graphical representation of a circuit design 有权电路设计的层次结构，连接性和图形表示的规范公开(公告)号：US07003751B1
公开(公告)日：2006-02-21
申请号：US10340498
申请日：2003-01-10
申请人： Jeffrey D. Stroomer , Roger B. Milne , Jonathan B. Ballagh , Haibing Ma , L. James Hwang , Nabeel Shirazi
发明人： Jeffrey D. Stroomer , Roger B. Milne , Jonathan B. Ballagh , Haibing Ma , L. James Hwang , Nabeel Shirazi
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Method and apparatus for creating a circuit design. An object-oriented program instantiates a plurality of objects that model a circuit design. The objects have hierarchy attributes, connectivity attributes, and display attributes that describe a plurality of modules. The hierarchy attributes define parent-child relationships between modules, the connectivity attributes define input-output connections between modules, and the display attributes define a layout of the modules for viewing. Each of the objects has an associated method for generating a design specification in a selected format. When the program is executed, the design specification is generated from the set of objects. Depending on the capabilities of the available tools, the modules and logic elements are displayed in accordance with the display attributes either from the object-oriented program or from the design specification.
摘要翻译： 用于创建电路设计的方法和装置。 面向对象的程序实例化建模电路设计的多个对象。 对象具有描述多个模块的层次属性，连接属性和显示属性。 层次结构属性定义模块之间的父子关系，连接属性定义模块之间的输入输出连接，显示属性定义模块的布局以供查看。 每个对象具有用于以所选格式生成设计规范的关联方法。 当执行程序时，设计规范是从对象集合生成的。 根据可用工具的功能，根据面向对象程序或设计规范的显示属性显示模块和逻辑元素。
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公开(公告)号：US07207015B1
公开(公告)日：2007-04-17
申请号：US10618037
申请日：2003-07-11
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Translation of an electronic design of an integrated circuit into circuit description language is described. In an example, a connection among circuit descriptions representing behavior of circuit elements in the electronic design is identified. The connection is associated with an identifier. The electronic design is then translated into a circuit description language representation, where the connection is implemented within the circuit description language representation using the identifier. In another example, an implicit circuit description representing behavior of circuit elements within the electronic design are identified. Explicit circuit descriptions within the electronic design are augmented with an addition circuit description. The electronic design is then translated into a circuit description language representation.
摘要翻译： 将集成电路的电子设计翻译成电路描述语言。 在一个示例中，识别表示电子设计中电路元件的行为的电路描述之间的连接。 连接与标识符相关联。 然后将电子设计转换成电路描述语言表示，其中使用标识符在电路描述语言表示内实现连接。 在另一示例中，识别表示电子设计内的电路元件的行为的隐式电路描述。 电子设计中的显式电路描述增加了加法电路描述。 然后将电子设计转换为电路描述语言表示。
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5.发明授权Translation of an electronic integrated circuit design into hardware description language using circuit description template 有权将电子集成电路设计翻译成使用电路描述模板的硬件描述语言公开(公告)号：US07007261B1
公开(公告)日：2006-02-28
申请号：US10388711
申请日：2003-03-14
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Method, apparatus, and computer readable medium for translating an electronic design of an integrated circuit into circuit description language is described. The electronic design includes a plurality of circuit descriptions representing behavior of circuit elements. A circuit description template is associated with a circuit description of the plurality of circuit descriptions. The circuit description template includes a first portion for fixed attributes of the circuit description and a second portion for variable attributes of the circuit description. One or more text processors are associated with the circuit description template. Variable attributes of the circuit description are related to the second portion of the circuit description template to produce a data structure. The circuit description template is processed using the one or more text processors with the data structure as parametric input.
摘要翻译： 描述了用于将集成电路的电子设计转换为电路描述语言的方法，装置和计算机可读介质。 电子设计包括表示电路元件的行为的多个电路描述。 电路描述模板与多个电路描述的电路描述相关联。 电路描述模板包括用于电路描述的固定属性的第一部分和用于电路描述的可变属性的第二部分。 一个或多个文本处理器与电路描述模板相关联。 电路描述的可变属性与电路描述模板的第二部分相关，以产生数据结构。 使用具有数据结构作为参数输入的一个或多个文本处理器来处理电路描述模板。
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公开(公告)号：US07478030B1
公开(公告)日：2009-01-13
申请号：US10600848
申请日：2003-06-19
CPC分类号： G06F17/5027 , G06F2217/62
摘要： Method and apparatus for clock stabilization detection for hardware simulation is described. More particularly, a lock signal is obtained, for example from a digital clock module. A least common multiple (LCM) clock signal is generated, for example from a clock module. A control signal is generated at least partially responsive to the LCM clock signal and the lock signal. The control signal may be generated from a state machine and applied to select circuitry, where the control signal is used to mask application of the output clock signal responsive to the control signal.
摘要翻译： 描述了用于硬件模拟的时钟稳定检测的方法和装置。 更具体地，例如从数字时钟模块获得锁定信号。 例如从时钟模块产生最小公共多（LCM）时钟信号。 至少部分地响应于LCM时钟信号和锁定信号产生控制信号。 控制信号可以从状态机产生并应用于选择电路，其中控制信号用于响应于控制信号屏蔽输出时钟信号的应用。
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7.发明授权公开(公告)号：US07437280B1
公开(公告)日：2008-10-14
申请号：US11016378
申请日：2004-12-16
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F2217/86
摘要： Co-simulation of an electronic circuit design using an embedded processor on a programmable logic device (PLD). The programmable logic resources of a PLD are used to perform hardware-based co-simulation of a first portion of the electronic circuit design. Software-based co-simulation of a second portion of the electronic circuit design is performed using the embedded processor.
摘要翻译： 使用可编程逻辑器件（PLD）上的嵌入式处理器进行电子电路设计的协同仿真。 PLD的可编程逻辑资源用于执行电子电路设计的第一部分的基于硬件的协同仿真。 使用嵌入式处理器执行电子电路设计的第二部分的基于软件的协同仿真。
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公开(公告)号：US07363600B1
公开(公告)日：2008-04-22
申请号：US10691343
申请日：2003-10-21
CPC分类号： G06F17/5022
摘要： A method of modeling a design in a high level modeling system that supports unidirectional data flow, may comprise identifying a bus-block to represent a connectivity of a bi-directional bus in an system. The bus-block may be represented in serial relationship with the bus. Taps may interface the bus via the bus-block. During simulation, the bus-block emulates behavior of a tri-state buffer in series with an input line for the tap interface. During synthesis, pairs of unidirectional input and output lines of opposite data-routing orientation, which may emulate bus ports to the bus-block, may be collapsed to a single bus port. The synthesis may further generate a netlist that may dispose a tri-state buffer between a tap input and the bus. The netlist may also represent layout of the tri-state buffer for driving an output of the tap.
摘要翻译： 在支持单向数据流的高级建模系统中对设计建模的方法可以包括识别总线块以表示系统中双向总线的连接性。 总线块可以与总线串联表示。 分接头可以通过总线接口连接总线。 在仿真期间，总线模块仿真与分接口的输入线串联的三态缓冲器的行为。 在合成期间，可以模拟总线端口到总线块的相反数据路由取向的单向输入和输出线对可以被折叠到单个总线端口。 该合成可以进一步生成可以在抽头输入和总线之间设置三态缓冲器的网表。 网表还可以表示用于驱动水龙头输出的三态缓冲器的布局。
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公开(公告)号：US07086030B1
公开(公告)日：2006-08-01
申请号：US10633830
申请日：2003-08-04
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/86
摘要： Method and apparatus for preparing a design in a high-level modeling system. Hardware description language (HDL) code is generated for one or more of a plurality of high-level subsystems in a high-level design tagged by the user for HDL code generation. Previously generated HDL code may be reused instead of generating new HDL code for each subsystem tagged by the user for HDL code reuse.
摘要翻译： 用于在高级建模系统中准备设计的方法和装置。 为由HDL代码生成用户标记的高级设计中的多个高级子系统中的一个或多个生成硬件描述语言（HDL）代码。 以前生成的HDL代码可以被重用，而不是为用户为HDL代码重用标记的每个子系统生成新的HDL代码。
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10.发明授权Shared memory interface in a programmable logic device using partial reconfiguration 有权使用部分重新配置的可编程逻辑器件中的共享存储器接口公开(公告)号：US07546572B1
公开(公告)日：2009-06-09
申请号：US11230879
申请日：2005-09-20
IPC分类号： H03K17/693
CPC分类号： H03K19/17756 , H03K19/17732 , H03K19/1776
摘要： Partial reconfiguration of a programmable logic device is used in combination with a shared memory block for communicating between two blocks of an electronic circuit design. In one embodiment, a shared memory is implemented on RAM resources of a field programmable gate array (FPGA), and a first design block implemented in resources of the FPGA is coupled to the shared memory. A second design block is also coupled to the shared memory. In response to a write request by the second design block, a process determines the RAM resources of the FPGA that correspond to the shared memory address in the write request. A configuration bitstream is generated to include configuration data for partial reconfiguration of the FPGA with the data from the write request at the appropriate RAM resources. The FPGA is partially reconfigured with the configuration bitstream via a configuration port of the FPGA.
摘要翻译： 可编程逻辑器件的部分重新配置与用于在电子电路设计的两个块之间进行通信的共享存储器块结合使用。 在一个实施例中，在现场可编程门阵列（FPGA）的RAM资源上实现共享存储器，并且在FPGA的资源中实现的第一设计块耦合到共享存储器。 第二设计块也耦合到共享存储器。 响应于第二设计块的写请求，处理确定与写请求中的共享存储器地址相对应的FPGA的RAM资源。 生成配置比特流以包括用于使用来自写入请求的数据在适当的RAM资源处对FPGA进行部分重新配置的配置数据。 FPGA通过FPGA的配置端口部分配置配置比特流。
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