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    Process of routing tile-to-tile interconnects of an FPGA, and method of manufacturing an FPGA
    1.
    发明授权
    Process of routing tile-to-tile interconnects of an FPGA, and method of manufacturing an FPGA 有权

    公开(公告)号：US11916551B2

    公开(公告)日：2024-02-27

    申请号：US17676123

    申请日：2022-02-19

    申请人： Flex Logix Technologies, Inc.

    发明人： Yongning Liu ,  Fan Mo ,  Cheng C. Wang

    IPC分类号： H03K19/17736 ,  H03K19/17796 ,  H03K19/17732

    CPC分类号： H03K19/17744 ,  H03K19/17732 ,  H03K19/17796

    摘要： A method of routing interconnects of a field programmable gate array including: a plurality of logic tiles, and a tile-to-tile interconnect network, having a plurality of tile-to-tile interconnects to interconnect logic tile networks of the logic tiles, the method comprises: routing a first plurality of tile-to-tile interconnects in a first plurality of logic tiles. After routing the first plurality of tile-to-tile interconnects, routing a second plurality of tile-to-tile interconnects in a second plurality of logic tiles. The start/end point of each tile-to-tile interconnect in the first plurality and the second plurality of tiles is independent of the start/end point of the other tile-to-tile interconnects in the first and second plurality, respectively. Routing the second plurality of tile-to-tile interconnects includes connecting at least one start/end point of each tile-to-tile interconnect in the second plurality of tiles to at least one start/end point of each interconnect in the first plurality of tiles.

    EFFICIENT CONSTANT MULTIPLIER IMPLEMENTATION FOR PROGRAMMABLE LOGIC DEVICES
    5.
    发明申请
    EFFICIENT CONSTANT MULTIPLIER IMPLEMENTATION FOR PROGRAMMABLE LOGIC DEVICES 有权
    针对可编程逻辑器件的高效持续执行

    公开(公告)号：US20150378682A1

    公开(公告)日：2015-12-31

    申请号：US14316049

    申请日：2014-06-26

    申请人： Lattice Semiconductor Corporation

    发明人： Sunil Kumar Sharma ,  Mohana Tandyala

    IPC分类号： G06F7/575 ,  G06F5/01

    CPC分类号： G06F5/01 ,  G06F7/527 ,  G06F17/5054 ,  H03K19/17732

    摘要： Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD and synthesizing the design into a plurality of PLD components. The synthesizing includes detecting a constant multiplier operation in the design, determining a nearest boundary condition for the constant multiplier operation, and decomposing the constant multiplier operation using the nearest boundary condition to reduce the plurality of PLD components. The reduced plurality of PLD components comprise at least one look up table (LUT) configured to implement an addition or subtraction operation of the decomposed constant multiplier operation.

    摘要翻译： 提供了各种技术来有效地实现可编程逻辑器件（PLD）中的用户设计。 在一个示例中，计算机实现的方法包括接收由PLD执行的操作的设计，并将该设计合成为多个PLD组件。 该合成包括检测设计中的常数乘法运算，确定常数乘法运算的最近边界条件，以及使用最近边界条件分解常数乘法器运算以减少多个PLD分量。 减少的多个PLD分量包括被配置为实现分解的常数乘法器操作的加法或减法运算的至少一个查询表（LUT）。

    Adaptive interface for coupling FPGA modules
    6.
    发明授权
    Adaptive interface for coupling FPGA modules 有权
    用于耦合FPGA模块的自适应接口

    公开(公告)号：US09160338B2

    公开(公告)日：2015-10-13

    申请号：US14275284

    申请日：2014-05-12

    申请人： dSPACE digital signal processing and control engineering GmbH

    发明人： Dirk Hasse ,  Robert Polnau

    IPC分类号： H03K19/173 ,  H03K19/177 ,  G06F7/38 ,  H03K19/0175 ,  G06F13/42

    CPC分类号： H03K19/017509 ,  G06F13/4291 ,  H03K19/0175 ,  H03K19/17732 ,  H03K19/17744

    摘要： A method for implementing an adaptive interface between at least one FPGA with at least one FPGA application and at least one I/O module, which are designed as the corresponding sender side or receiver side, for connection to the FPGA, whereby a serial interface is formed between the at least one FPGA and the at least one I/O module, comprising the steps of configuring a maximum number of registers to be transmitted for each FPGA application, configuring a shared, fixed register width for all registers, setting an enable signal on the sender side for the registers to be transmitted out of the maximum number of registers to be transmitted, transmitting the enable signal from the sender side to the receiver side, and transmitting the registers, for which the enable signal is set, from the sender side to the receiver side.

    摘要翻译： 一种在至少一个FPGA与至少一个FPGA应用之间实现自适应接口的方法和被设计为相应的发送机侧或接收机侧的至少一个I / O模块，用于连接到FPGA，由此串行接口是 形成在所述至少一个FPGA和所述至少一个I / O模块之间，包括以下步骤：配置要针对每个FPGA应用发送的最大寄存器数量，为所有寄存器配置共享固定寄存器宽度，设置使能信号 在发送侧，要发送的寄存器的最大数量的寄存器发送，将发送端发送到接收端，并从发送方发送启用信号的寄存器 侧到接收机侧。

    Configuration context switcher with a clocked storage element
    9.
    发明授权
    Configuration context switcher with a clocked storage element 有权
    具有时钟存储元件的配置上下文切换器

    公开(公告)号：US08598907B2

    公开(公告)日：2013-12-03

    申请号：US13360646

    申请日：2012-01-27

    申请人： Trevis Chandler ,  Joe Entjer ,  Martin Voogel ,  Jason Redgrave

    发明人： Trevis Chandler ,  Joe Entjer ,  Martin Voogel ,  Jason Redgrave

    IPC分类号： H03K19/173

    CPC分类号： H03K19/0008 ,  G06F15/7867 ,  G11C7/1045 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H03K3/0372 ,  H03K19/17732 ,  H03K19/17748 ,  H03K19/17752 ,  H03K19/17768 ,  H01L2924/00 ,  H01L2924/00014

    摘要： Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data.

    摘要翻译： 一些实施例向IC提供配置上下文切换器。 IC包括几个可配置电路，每个可配置电路可以在任何给定时间根据当时接收到的配置数据集配置执行多个操作之一。 IC包括多个存储电路，用于存储每个可配置电路的几个配置数据组。 IC还包括用于将可配置电路可切换地连接到不同组的存储电路以接收不同组的配置数据集的上下文切换互连电路。 上下文切换器包括用于重新定时来自配置存储元件的数据的一个或多个阶段。 这些阶段可以包括互连电路或存储电路。 一些实施例构建配置数据存储元件中的一个阶段。 一些实施例对配置数据位进行编码，并因此利用上下文切换器中的解码器对编码的配置数据进行解码。