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1.发明授权High reliability triple redundant latch with voting logic on each storage node 失效每个存储节点上具有投票逻辑的高可靠性三重冗余锁存器公开(公告)号：US07179690B2
公开(公告)日：2007-02-20
申请号：US11074526
申请日：2005-03-07
CPC分类号： H03K3/0375
摘要： In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, three voting structures with inputs from the first, second, and third settable memory elements and control to the settable memory elements determine the logical values held on the settable memory elements. The propagation delay through a latch is the only propagation delay of the triple redundant latch.
摘要翻译： 在优选实施例中，本发明提供了一种用于高可靠性三重冗余锁存器的电路和方法。 三个可设置的存储器元件将相同的逻辑值设置到每个可设置的存储器元件中。 在可设置的存储器元件被设置之后，具有来自第一，第二和第三可设置存储器元件的输入的三个投票结构以及对可设置的存储器元件的控制确定保持在可设置的存储器元件上的逻辑值。 通过锁存器的传播延迟是三重冗余锁存器的唯一传播延迟。
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公开(公告)号：US07215581B2
公开(公告)日：2007-05-08
申请号：US10825398
申请日：2004-04-14
CPC分类号： H03K3/0375
摘要： In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, a voting structure with inputs from the first settable memory element, the second memory element, and control to the settable memory elements determines the logical value held on the third settable memory element. The propagation delay through the third settable memory element is the only propagation delay of the triple redundant latch.
摘要翻译： 在优选实施例中，本发明提供了一种用于更小和更快的三重冗余锁存器的电路和方法。 三个可设置的存储器元件将相同的逻辑值设置到每个可设置的存储器元件中。 在可设置的存储器元件被设置之后，具有来自第一可设定存储元件，第二存储器元件的输入和对可设置存储器元件的控制的投票结构确定保持在第三可设置存储器元件上的逻辑值。 通过第三可设置存储元件的传播延迟是三重冗余锁存器的唯一传播延迟。
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公开(公告)号：US07054203B2
公开(公告)日：2006-05-30
申请号：US10834627
申请日：2004-04-28
IPC分类号： G11C7/10
CPC分类号： H03K3/0375
摘要： In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch. Two settable memory elements, and a voting structure/settable memory element set an identical logical value into each settable memory element, and the voting structure/settable memory element. After the settable memory elements, and the voting structure/settable memory element are set, the voting structure/settable memory element with inputs from the first settable memory element, the second memory element, and control to the settable memory elements determines the logical value held on the voting structure/settable memory element. The propagation delay through the voting structure/settable memory element is the only propagation delay of the triple redundant latch.
摘要翻译： 在优选实施例中，本发明提供了一种用于更小和更快的三重冗余锁存器的电路和方法。 两个可设置的存储器元件和投票结构/可设置存储元件将相同的逻辑值设置到每个可设置的存储元件中，以及投票结构/可设置存储元件。 在可设置的存储器元件和投票结构/可设置存储元件被设置之后，具有来自第一可设定存储元件，第二存储器元件的输入和对可设置存储器元件的控制的投票结构/可设置存储元件确定保持的逻辑值 在投票结构/可设置的记忆元素上。 通过投票结构/可设置存储元件的传播延迟是三重冗余锁存器的唯一传播延迟。
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4.发明授权High reliability triple redundant latch with voting logic on each storage node 失效每个存储节点上具有投票逻辑的高可靠性三重冗余锁存器公开(公告)号：US06937527B1
公开(公告)日：2005-08-30
申请号：US10856557
申请日：2004-05-27
CPC分类号： H03K3/0375
摘要： In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, three voting structures with inputs from the first, second, and third settable memory elements and control to the settable memory elements determine the logical values held on the settable memory elements. The propagation delay through a latch is the only propagation delay of the triple redundant latch.
摘要翻译： 在优选实施例中，本发明提供了一种用于高可靠性三重冗余锁存器的电路和方法。 三个可设置的存储器元件将相同的逻辑值设置到每个可设置的存储器元件中。 在可设置的存储器元件被设置之后，具有来自第一，第二和第三可设置存储器元件的输入的三个投票结构以及对可设置的存储器元件的控制确定保持在可设置的存储器元件上的逻辑值。 通过锁存器的传播延迟是三重冗余锁存器的唯一传播延迟。
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公开(公告)号：US06930527B1
公开(公告)日：2005-08-16
申请号：US10769337
申请日：2004-01-30
CPC分类号： H03K3/0375
摘要： In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch with storage node recovery. An input driver is connected to the input of three transfer gates. The output of each transfer gate is connected to a separate output of one of three feedback inverters. The transfer gates are controlled by two control inputs. The inputs of the three feedback inverters are connected the output of the forward inverter/majority voter. The output from each of the three feedback inverters are inputs to the forward inverter/majority voter. The output of the forward inverter/majority voter is connected to the input of the output driver. The output of the output driver is the output of the triple redundant latch.
摘要翻译： 在优选实施例中，本发明提供了一种用于具有存储节点恢复的较小且更快的三重冗余锁存器的电路和方法。 输入驱动器连接到三个传输门的输入端。 每个传输门的输出连接到三个反馈逆变器之一的单独输出。 传输门由两个控制输入控制。 三个反馈逆变器的输入端连接在正向逆变器/多数选择器的输出端。 三个反馈逆变器中的每一个的输出是正向逆变器/多数选择器的输入。 正向逆变器/多数选择器的输出端连接到输出驱动器的输入端。 输出驱动器的输出是三重冗余锁存器的输出。
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6.发明授权公开(公告)号：US06882201B1
公开(公告)日：2005-04-19
申请号：US10754075
申请日：2004-01-07
CPC分类号： H03K3/0375
摘要： In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch. An input driver is connected to the input of two transfer gates. The output of one transfer gate is connected to an I/O of a first latch and the output of the second transfer gate is connected to the I/O of a second latch. The I/O of the first latch is connected to a first input of a tristatable input inverter. The I/O of the second latch is connected to a second input of the tristatable input inverter. The output of the tristatable input inverter is connected to the I/O of a third latch and the input of an output driver.
摘要翻译： 在优选实施例中，本发明提供了一种用于更小和更快的三重冗余锁存器的电路和方法。 输入驱动器连接到两个传输门的输入端。 一个传输门的输出连接到第一锁存器的I / O，第二传输门的输出端连接到第二锁存器的I / O。 第一锁存器的I / O连接到可跟踪输入反相器的第一输入端。 第二锁存器的I / O连接到可跟踪输入反相器的第二输入端。 可跟踪输入反相器的输出端连接到第三个锁存器的I / O和输出驱动器的输入端。
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