公开(公告)号：US06507224B1

公开(公告)日：2003-01-14

申请号：US10038171

申请日：2002-01-03

申请人： Jong Cheol Lee ,  Yong Jin Yoon ,  Kwang Jin Lee

发明人： Jong Cheol Lee ,  Yong Jin Yoon ,  Kwang Jin Lee

IPC分类号： G11C2702

CPC分类号： H03K3/356139 ,  H03K3/012 ,  H03K3/356156

摘要： An input receiver capable of sensing and amplifying an external signal having a very small swing input signal. The input receiver comprises a clock sampled amplifier for receiving a clock signal and a reference signal, respectively, in response to a first state of a clock signal and a delayed sampling clock signal, and for amplifying and sampling the voltage difference between the external signal and the reference signal, respectively, in response to a transition of the clock and delayed sampling clock signals to a second state; and a pulse generator for pre-charging a power source voltage and selectively pulling down the pre-charged signals to produce a pulse signal, in response to the second state of the delayed sampling clock signal and outputs of the clock sampled amplifier.

摘要翻译： 一种能够感测和放大具有非常小的摆动输入信号的外部信号的输入接收器。 输入接收机包括响应于时钟信号和延迟采样时钟信号的第一状态分别接收时钟信号和参考信号的时钟采样放大器，并且用于放大和采样外部信号与 分别响应于时钟的转变和延迟的采样时钟信号到第二状态的参考信号; 以及脉冲发生器，用于响应于延迟的采样时钟信号的第二状态和时钟采样放大器的输出，对电源电压进行预充电并选择性地拉低预充电信号以产生脉冲信号。

公开(公告)号：US08885394B2

公开(公告)日：2014-11-11

申请号：US13604743

申请日：2012-09-06

申请人： Byung-Ho Kang ,  Yong Jin Yoon ,  Young Jae Son

发明人： Byung-Ho Kang ,  Yong Jin Yoon ,  Young Jae Son

IPC分类号： G11C11/00 ,  G11C7/12 ,  G11C7/18 ,  G11C11/419

CPC分类号： G11C11/419 ,  G11C7/12 ,  G11C7/18

摘要： A memory device includes sections arranged between a global bit line and a complementary global bit line, and having a section control unit disposed between first and second memory cell groups and connected between the global bit line and the complementary global bit line to provide a first read signal and a second read signal. A signal converter receives the first and second read signals and generates a stable controlled read signal indicative of a data value stored in the memory cell. A latch unit receives and latches the controlled read signal provided by the signal converter to generate a latched read signal.

摘要翻译： 存储器件包括布置在全局位线和互补全局位线之间的部分，并且具有设置在第一和第二存储器单元组之间并连接在全局位线和互补全局位线之间的部分控制单元，以提供第一读取 信号和第二读信号。 信号转换器接收第一和第二读取信号，并产生指示存储在存储单元中的数据值的稳定受控读取信号。 锁存单元接收并锁存由信号转换器提供的受控读信号以产生锁存的读信号。