System and Method for Dynamically Adjusting Read Ahead Values Based Upon Memory Usage
    1.
    发明申请
    System and Method for Dynamically Adjusting Read Ahead Values Based Upon Memory Usage 失效
    基于内存使用动态调整读取前值的系统和方法

    公开(公告)号:US20060288186A1

    公开(公告)日:2006-12-21

    申请号:US11463100

    申请日:2006-08-08

    IPC分类号: G06F12/00

    CPC分类号: G06F12/023

    摘要: A system and method for dynamically altering a Virtual Memory Manager (VMM) Sequential-Access Read Ahead settings based upon current system memory conditions is provided. Normal VMM operations are performed using the Sequential-Access Read Ahead values set by the user. When low memory is detected, the system either turns off Sequential-Access Read Ahead operations or decreases the maximum page ahead (maxpgahead) value based upon whether the amount of free space is simply low or has reached a critically low level. The altered VMM Sequential-Access Read Ahead state remains in effect until enough free space is available so that normal VMM Sequential-Access Read Ahead operations can be performed (at which point the altered Sequential-Access Read Ahead values are reset to their original levels).

    摘要翻译: 提供了一种基于当前系统内存条件动态更改虚拟内存管理器(VMM)顺序访问预读设置的系统和方法。 使用用户设置的顺序访问读取前值可以执行正常的VMM操作。 当检测到低内存时,系统会根据自由空间量是否很低或已经达到极低的水平,关闭顺序访问预读操作或者减小最大页面前提(maxpgahead)值。 改变的VMM顺序访问预读状态在有足够的可用空间可用之前保持有效,以便可以执行正常的VMM顺序访问预读操作(此时,改变的顺序访问读取前置值被重置为其原始级别) 。

    Administration of locks for critical sections of computer programs in a computer that supports a multiplicity of logical partitions
    2.
    发明申请
    Administration of locks for critical sections of computer programs in a computer that supports a multiplicity of logical partitions 失效
    在支持多个逻辑分区的计算机中管理计算机程序的关键部分的锁

    公开(公告)号:US20060277551A1

    公开(公告)日:2006-12-07

    申请号:US11146453

    申请日:2005-06-06

    IPC分类号: G06F9/46

    CPC分类号: G06F9/526 G06F9/5077

    摘要: Administration of locks for critical sections of computer programs in a computer that supports a multiplicity of logical partitions that include determining by a thread executing on a virtual processor executing in a time slice on a physical processor whether an expected lock time for a critical section of the thread exceeds a remaining entitlement of the virtual processor in the time slice and deferring acquisition of a lock if the expected lock time exceeds the remaining entitlement.

    摘要翻译: 管理计算机中计算机程序的关键部分的锁,其支持多个逻辑分区,所述逻辑分区包括由在物理处理器上的时间片中执行的在虚拟处理器上执行的线程来确定是否预期的锁定时间 线程超过了时间片中虚拟处理器的剩余权限,如果预期的锁定时间超过剩余权限,则推迟获取锁定。

    Nodelay per port
    3.
    发明申请
    Nodelay per port 失效
    Nodelay每口

    公开(公告)号:US20060047848A1

    公开(公告)日:2006-03-02

    申请号:US10860409

    申请日:2004-06-03

    IPC分类号: G06F15/173

    CPC分类号: H04L67/322

    摘要: Methods, systems, and media are disclosed for improved granularity of a response-request communication on a networked computer system. One example embodiment includes receiving the request-response communication by the networked computer system, and associating the request-response communication with a port, having a nodelay setting, from a set of ports on the networked computer system. Further, the example embodiment includes enabling, based upon the associating, the nodelay setting upon connection of the request-response communication with the port. Further still, the example embodiment includes sending, in accordance with the enabling, the request-response communication to a destination in communication with the networked computer system. In addition, further example embodiments include configuring the ports on the networked computer system with nodelay values indicating whether a particular port is assigned nodelay or no nodelay for a request portion or request portion of a request-response communication connecting to that particular port.

    摘要翻译: 公开了用于网络计算机系统上的响应请求通信的粒度的方法,系统和媒体。 一个示例性实施例包括:由联网计算机系统接收请求 - 响应通信,并且从联网计算机系统上的一组端口将请求响应通信与具有节日设置的端口相关联。 此外,示例性实施例包括在连接请求响应通信与端口时基于关联启用节目设置。 此外,示例实施例包括根据启用的方式向与联网的计算机系统通信的目的地发送请求 - 响应通信。 另外,进一步的示例性实施例包括在网络计算机系统上配置端口,其中节点值指示特定端口是否被分配了节目,或者没有连接到该特定端口的请求响应通信的请求部分或请求部分。

    System, apparatus and method of reducing adverse performance impact due to migration of processes from one CPU to another
    4.
    发明申请
    System, apparatus and method of reducing adverse performance impact due to migration of processes from one CPU to another 审中-公开
    减少由一个CPU向另一个CPU迁移的不利性能影响的系统,设备和方法

    公开(公告)号:US20060037017A1

    公开(公告)日:2006-02-16

    申请号:US10916985

    申请日:2004-08-12

    IPC分类号: G06F9/46

    CPC分类号: G06F9/5088

    摘要: A system, apparatus and method of reducing adverse performance impact due to migration of processes from one processor to another in a multi-processor system are provided. When a process is executing, the number of cycles it takes to fetch each instruction (CPI) of the process is stored. After execution of the process, an average CPI is computed and stored in a storage device that is associated with the process. When a run queue of the multi-processor system is empty, a process may be chosen from the run queue that has the most processes awaiting execution to migrate to the empty run queue. The chosen process is the process that has the highest average number of CPIs.

    摘要翻译: 提供了一种在多处理器系统中减少由于处理器从一个处理器迁移到另一个处理器的不利性能影响的系统,装置和方法。 当进程正在执行时,存储获取进程的每个指令(CPI)所需的周期数。 在执行该过程之后,计算平均CPI并将其存储在与该过程相关联的存储设备中。 当多处理器系统的运行队列为空时,可以从运行队列中选择具有等待执行的最多进程迁移到空运行队列的进程。 所选择的过程是具有最高平均CPI值的过程。

    Scheduling threads in a multi-processor computer
    5.
    发明申请
    Scheduling threads in a multi-processor computer 审中-公开
    在多处理器计算机中调度线程

    公开(公告)号:US20050246461A1

    公开(公告)日:2005-11-03

    申请号:US10834498

    申请日:2004-04-29

    IPC分类号: G06F9/48 G06F12/14

    CPC分类号: G06F9/4812

    摘要: Scheduling threads in a multi-processor computer system including establishing an interrupt threshold for a thread, where the interrupt threshold represents a maximum permissible number of interrupts during thread execution on a processor; executing the thread on a current processor, where the thread has thread affinity for one or more processors including the current processor; counting a number of interrupts during execution of the thread on the current processor; and removing thread affinity for the current processor in dependence upon the counted number of interrupts and the interrupt threshold.

    摘要翻译: 在多处理器计算机系统中调度线程,包括建立线程的中断阈值,其中中断阈值表示在处理器上执行线程期间的最大允许中断次数; 在当前处理器上执行线程,其中线程对于包括当前处理器的一个或多个处理器具有线程亲和性; 在当前处理器上的线程执行期间对多个中断进行计数; 并根据计数的中断次数和中断阈值去除当前处理器的线程亲和度。

    Method and apparatus for aging data in a cache
    6.
    发明授权
    Method and apparatus for aging data in a cache 有权
    用于在缓存中老化数据的方法和装置

    公开(公告)号:US07337276B2

    公开(公告)日:2008-02-26

    申请号:US11201642

    申请日:2005-08-11

    IPC分类号: G06F12/00

    CPC分类号: G06F12/0897 G06F12/0891

    摘要: A computer implemented method, apparatus, and computer usable code for managing cache data. A partition identifier is associated with a cache entry in a cache, wherein the partition identifier identifies a last partition accessing the cache entry. The partition identifier associated with the cache entry is compared with a previous partition identifier located in a processor register in response to the cache entry being moved into a lower level cache relative to the cache. The cache entry is marked if the partition identifier associated with the cache entry matches the previous partition identifier located in the processor register to form a marked cache entry, wherein the marked cache entry is aged at a slower rate relative to an unmarked cache entry.

    摘要翻译: 计算机实现的方法,装置和用于管理高速缓存数据的计算机可用代码。 分区标识符与高速缓存中的高速缓存条目相关联,其中分区标识符标识访问高速缓存条目的最后一个分区。 与高速缓存条目相关联的分区标识符与位于处理器寄存器中的先前分区标识符进行比较,以响应于高速缓存条目相对于高速缓存移动到较低级高速缓存。 如果与高速缓存条目相关联的分区标识与位于处理器寄存器中的先前分区标识符相匹配以形成标记的高速缓存条目,则标记高速缓存条目,其中标记的高速缓存条目相对于未标记的高速缓存条目以较慢的速率进行老化。

    Method, computer program product, and data processing system for improving transaction-oriented client-server application performance
    7.
    发明申请
    Method, computer program product, and data processing system for improving transaction-oriented client-server application performance 审中-公开
    方法,计算机程序产品和数据处理系统,用于提高面向事务的客户端 - 服务器应用程序性能

    公开(公告)号:US20050265235A1

    公开(公告)日:2005-12-01

    申请号:US10855732

    申请日:2004-05-27

    IPC分类号: H04L1/18 H04L12/26

    CPC分类号: H04L1/1803

    摘要: A method, computer program product, and a data processing system for processing transactions of a client-server application is provided. A first data set is transmitted from a client to a server. A second data set to be transmitted to the server is received by the client. An evaluation is made to determine whether transmission of the second data set is blocked until receipt of an acknowledgment of the first data set. A number of allowable outstanding acknowledgements is increased responsive to determining that the second data set is blocked from transmission.

    摘要翻译: 提供了一种用于处理客户机 - 服务器应用的事务的方法,计算机程序产品和数据处理系统。 第一数据集从客户端发送到服务器。 要发送到服务器的第二数据集被客户端接收。 进行评估以确定在接收到第一数据集的确认之前是否阻止第二数据集的传输。 响应于确定第二数据集被阻止传输而允许的许多未决确认被增加。

    System and method for CPI scheduling on SMT processors
    8.
    发明申请
    System and method for CPI scheduling on SMT processors 有权
    SMT处理器CPI调度的系统和方法

    公开(公告)号:US20050086660A1

    公开(公告)日:2005-04-21

    申请号:US10671132

    申请日:2003-09-25

    IPC分类号: G06F9/46

    CPC分类号: G06F9/4881 G06F2209/483

    摘要: A system and method for identifying compatible threads in a Simultaneous Multithreading (SMT) processor environment is provided by calculating a performance metric, such as CPI, that occurs when two threads are running on the SMT processor. The CPI that is achieved when both threads were executing on the SMT processor is determined. If the CPI that was achieved is better than the compatibility threshold, then information indicating the compatibility is recorded. When a thread is about to complete, the scheduler looks at the run queue from which the completing thread belongs to dispatch another thread. The scheduler identifies a thread that is (1) compatible with the thread that is still running on the SMT processor (i.e., the thread that is not about to complete), and (2) ready to execute. The CPI data is continually updated so that threads that are compatible with one another are continually identified.

    摘要翻译: 通过计算在SMT处理器上运行两个线程时发生的性能度量(如CPI),可以提供用于识别同时多线程(SMT)处理器环境中的兼容线程的系统和方法。 确定在两个线程在SMT处理器上执行时实现的CPI。 如果实现的CPI优于兼容性阈值,则记录指示兼容性的信息。 当线程即将完成时,调度程序将查看完成线程所属的运行队列,以调度另一个线程。 调度程序标识(1)与SMT处理器上仍然运行的线程(即,即将完成的线程)兼容的线程,以及(2)准备执行。 持续更新CPI数据,以便不断地识别彼此兼容的线程。

    System and method for CPI load balancing in SMT processors
    9.
    发明申请
    System and method for CPI load balancing in SMT processors 失效
    SMT处理器中CPI负载平衡的系统和方法

    公开(公告)号:US20050081183A1

    公开(公告)日:2005-04-14

    申请号:US10671057

    申请日:2003-09-25

    IPC分类号: G06F9/44 G06F9/46

    CPC分类号: G06F9/5083

    摘要: A system and method for scheduling threads in a Simultaneous Multithreading (SMT) processor environment utilizing multiple SMT processors is provided. Poor performing threads that are being run on each of the SMT processors are identified. After being identified, the poor performing threads are moved to a different SMT processor. Data is captured regarding the performance of threads. In one embodiment, this data includes each threads' CPI value. When a thread is moved, data regarding the thread and its performance at the time it was moved is recorded along with a timestamp. The data regarding previous moves is used to determine whether a thread's performance is improved following the move.

    摘要翻译: 提供了一种利用多个SMT处理器的同时多线程(SMT)处理器环境中调度线程的系统和方法。 识别在每个SMT处理器上运行的执行不良线程。 被识别后,执行不良的线程被移动到不同的SMT处理器。 捕获关于线程性能的数据。 在一个实施例中,该数据包括每个线程的CPI值。 当线程移动时,与线程及其在移动时的性能相关的数据与时间戳一起被记录。 关于先前移动的数据用于确定线程的性能是否随着移动而改善。

    Apparatus for aging data in a cache
    10.
    发明授权
    Apparatus for aging data in a cache 有权
    用于在缓存中老化数据的装置

    公开(公告)号:US07475194B2

    公开(公告)日:2009-01-06

    申请号:US11968481

    申请日:2008-01-02

    IPC分类号: G06F12/00

    CPC分类号: G06F12/0897 G06F12/0891

    摘要: A computer implemented method, apparatus, and computer usable code for managing cache data. A partition identifier is associated with a cache entry in a cache, wherein the partition identifier identifies a last partition accessing the cache entry. The partition identifier associated with the cache entry is compared with a previous partition identifier located in a processor register in response to the cache entry being moved into a lower level cache relative to the cache. The cache entry is marked if the partition identifier associated with the cache entry matches the previous partition identifier located in the processor register to form a marked cache entry, wherein the marked cache entry is aged at a slower rate relative to an unmarked cache entry.

    摘要翻译: 计算机实现的方法,装置和用于管理高速缓存数据的计算机可用代码。 分区标识符与高速缓存中的高速缓存条目相关联,其中分区标识符标识访问高速缓存条目的最后一个分区。 与高速缓存条目相关联的分区标识符与位于处理器寄存器中的先前分区标识符进行比较,以响应于高速缓存条目相对于高速缓存移动到较低级高速缓存。 如果与高速缓存条目相关联的分区标识与位于处理器寄存器中的先前分区标识符相匹配以形成标记的高速缓存条目,则标记高速缓存条目,其中标记的高速缓存条目相对于未标记的高速缓存条目以较慢的速率进行老化。