公开(公告)号：US07475194B2

公开(公告)日：2009-01-06

申请号：US11968481

申请日：2008-01-02

申请人： Jos Accapadi ,  Andrew Dunshea ,  Greg R. Mewhinney ,  Mysore Sathyanaranyana Srinivas

发明人： Jos Accapadi ,  Andrew Dunshea ,  Greg R. Mewhinney ,  Mysore Sathyanaranyana Srinivas

IPC分类号： G06F12/00

CPC分类号： G06F12/0897 ,  G06F12/0891

摘要： A computer implemented method, apparatus, and computer usable code for managing cache data. A partition identifier is associated with a cache entry in a cache, wherein the partition identifier identifies a last partition accessing the cache entry. The partition identifier associated with the cache entry is compared with a previous partition identifier located in a processor register in response to the cache entry being moved into a lower level cache relative to the cache. The cache entry is marked if the partition identifier associated with the cache entry matches the previous partition identifier located in the processor register to form a marked cache entry, wherein the marked cache entry is aged at a slower rate relative to an unmarked cache entry.

摘要翻译： 计算机实现的方法，装置和用于管理高速缓存数据的计算机可用代码。 分区标识符与高速缓存中的高速缓存条目相关联，其中分区标识符标识访问高速缓存条目的最后一个分区。 与高速缓存条目相关联的分区标识符与位于处理器寄存器中的先前分区标识符进行比较，以响应于高速缓存条目相对于高速缓存移动到较低级高速缓存。 如果与高速缓存条目相关联的分区标识与位于处理器寄存器中的先前分区标识符相匹配以形成标记的高速缓存条目，则标记高速缓存条目，其中标记的高速缓存条目相对于未标记的高速缓存条目以较慢的速率进行老化。

公开(公告)号：US20080072228A1

公开(公告)日：2008-03-20

申请号：US11943649

申请日：2007-11-21

申请人： Jos Accapadi ,  Andrew Dunshea ,  Dirk Michel ,  James Van Fleet

发明人： Jos Accapadi ,  Andrew Dunshea ,  Dirk Michel ,  James Van Fleet

IPC分类号： G06F9/46

CPC分类号： G06F9/52 ,  G06F9/4818

摘要： A system and method is provided for delaying a priority boost of an execution thread. When a thread prepares to enter a critical section of code, such as when the thread utilizes a shared system resource, a user mode accessible data area is updated indicating that the thread is in a critical section and, if the kernel receives a preemption event, the priority boost that the thread should receive. If the kernel receives a preemption event before the thread finishes the critical section, the kernel applies the priority boost on behalf of the thread. Often, the thread will finish the critical section without having to have its priority actually boosted. If the thread does receive an actual priority boost then, after the critical section is finished, the kernel resets the thread's priority to a normal level.

摘要翻译： 提供了一种用于延迟执行线程的优先级提升的系统和方法。 当线程准备进入代码的关键部分时，例如当线程利用共享系统资源时，更新用户模式可访问数据区域，指示线程处于关键部分，并且如果内核接收到抢占事件， 线程应该接收的优先级提升。 如果内核在线程完成关键部分之前收到抢占事件，则内核将代表线程应用优先级提升。 通常，线程将完成关键部分，而无需实际提升优先级。 如果线程确实接收到实际的优先级提升，那么在关键部分完成之后，内核会将线程的优先级重置为正常级别。

公开(公告)号：US20060036810A1

公开(公告)日：2006-02-16

申请号：US10916984

申请日：2004-08-12

申请人： Jos Accapadi ,  Larry Brenner ,  Andrew Dunshea ,  Dirk Michel

发明人： Jos Accapadi ,  Larry Brenner ,  Andrew Dunshea ,  Dirk Michel

IPC分类号： G06F12/00 ,  G06F12/14

CPC分类号： G06F9/5027 ,  G06F2209/5018

摘要： A system, apparatus and method of reducing cache thrashing in a multi-processor with a shared cache executing a disruptive process (i.e., a thread that has a poor cache affinity or a large cache footprint) are provided. When a thread is dispatched for execution, a table is consulted to determine whether the dispatched thread is a disruptive thread. If so, a system idle process is dispatched to the processor sharing a cache with the processor executing the disruptive thread. Since the system idle process may not use data intensively, cache thrashing may be avoided.

摘要翻译： 提供了一种使用执行破坏性过程的共享高速缓存（即，具有差的缓存关联性或大的缓存占用空间的线程）的多处理器中的缓存颠簸的系统，装置和方法。 当一个线程被调度执行时，查询一个表以确定被调度的线程是否是一个中断线程。 如果是这样，系统空闲进程将被分配到与执行中断线程的处理器共享高速缓存的处理器。 由于系统空闲进程可能不会集中使用数据，因此可以避免缓存抖动。

公开(公告)号：US20050198386A1

公开(公告)日：2005-09-08

申请号：US10782668

申请日：2004-02-19

申请人： Jos Accapadi ,  Mathew Accapadi ,  William Britton ,  Andrew Dunshea ,  Dirk Michel

发明人： Jos Accapadi ,  Mathew Accapadi ,  William Britton ,  Andrew Dunshea ,  Dirk Michel

IPC分类号： G06F15/16

CPC分类号： H04L61/1511

摘要： Methods, systems, and products are disclosed for user defined preferred DNS routing that include mapping for a user in a data communications application a domain name of a network host to a network address for a preferred DNS server, wherein the preferred DNS server has a network address for the domain name; receiving from the user a request for access to a resource accessible through the network host; and routing to the preferred DNS server a DNS request for the network address of the network host, the DNS request including the domain name of the network host. In typical embodiments, mapping a domain name to a network address for a preferred DNS server is carried out by storing, through the data communication application, the domain name in association with the network address for a preferred DNS server in a data structure in computer memory.

摘要翻译： 公开了用于用户定义的优选DNS路由的方法，系统和产品，其包括将数据通信应用中的用户映射到网络主机的域名到优选DNS服务器的网络地址，其中优选DNS服务器具有网络 地址为域名; 从用户接收对通过网络主机可访问的资源的访问请求; 并将首选DNS服务器路由到网络主机的网络地址的DNS请求，DNS请求包括网络主机的域名。 在典型的实施例中，将域名映射到优选DNS服务器的网络地址是通过数据通信应用程序与计算机存储器中的数据结构中的优选DNS服务器的网络地址相关联地存储域名来执行的 。

公开(公告)号：US20060288186A1

公开(公告)日：2006-12-21

申请号：US11463100

申请日：2006-08-08

申请人： Jos Accapadi ,  Andrew Dunshea ,  Li Li ,  Grover Neuman ,  Mysore Srinivas ,  David Hepkin

发明人： Jos Accapadi ,  Andrew Dunshea ,  Li Li ,  Grover Neuman ,  Mysore Srinivas ,  David Hepkin

IPC分类号： G06F12/00

CPC分类号： G06F12/023

摘要： A system and method for dynamically altering a Virtual Memory Manager (VMM) Sequential-Access Read Ahead settings based upon current system memory conditions is provided. Normal VMM operations are performed using the Sequential-Access Read Ahead values set by the user. When low memory is detected, the system either turns off Sequential-Access Read Ahead operations or decreases the maximum page ahead (maxpgahead) value based upon whether the amount of free space is simply low or has reached a critically low level. The altered VMM Sequential-Access Read Ahead state remains in effect until enough free space is available so that normal VMM Sequential-Access Read Ahead operations can be performed (at which point the altered Sequential-Access Read Ahead values are reset to their original levels).

摘要翻译： 提供了一种基于当前系统内存条件动态更改虚拟内存管理器（VMM）顺序访问预读设置的系统和方法。 使用用户设置的顺序访问读取前值可以执行正常的VMM操作。 当检测到低内存时，系统会根据自由空间量是否很低或已经达到极低的水平，关闭顺序访问预读操作或者减小最大页面前提（maxpgahead）值。 改变的VMM顺序访问预读状态在有足够的可用空间可用之前保持有效，以便可以执行正常的VMM顺序访问预读操作（此时，改变的顺序访问读取前置值被重置为其原始级别） 。

公开(公告)号：US20060277551A1

公开(公告)日：2006-12-07

申请号：US11146453

申请日：2005-06-06

申请人： Jos Accapadi ,  Andrew Dunshea ,  Sujatha Kashyap

发明人： Jos Accapadi ,  Andrew Dunshea ,  Sujatha Kashyap

IPC分类号： G06F9/46

CPC分类号： G06F9/526 ,  G06F9/5077

摘要： Administration of locks for critical sections of computer programs in a computer that supports a multiplicity of logical partitions that include determining by a thread executing on a virtual processor executing in a time slice on a physical processor whether an expected lock time for a critical section of the thread exceeds a remaining entitlement of the virtual processor in the time slice and deferring acquisition of a lock if the expected lock time exceeds the remaining entitlement.

摘要翻译： 管理计算机中计算机程序的关键部分的锁，其支持多个逻辑分区，所述逻辑分区包括由在物理处理器上的时间片中执行的在虚拟处理器上执行的线程来确定是否预期的锁定时间 线程超过了时间片中虚拟处理器的剩余权限，如果预期的锁定时间超过剩余权限，则推迟获取锁定。

公开(公告)号：US20060047848A1

公开(公告)日：2006-03-02

申请号：US10860409

申请日：2004-06-03

申请人： Jos Accapadi ,  Kavitha Baratakke ,  Andrew Dunshea ,  Venkat Venkatsubra

发明人： Jos Accapadi ,  Kavitha Baratakke ,  Andrew Dunshea ,  Venkat Venkatsubra

IPC分类号： G06F15/173

CPC分类号： H04L67/322

摘要： Methods, systems, and media are disclosed for improved granularity of a response-request communication on a networked computer system. One example embodiment includes receiving the request-response communication by the networked computer system, and associating the request-response communication with a port, having a nodelay setting, from a set of ports on the networked computer system. Further, the example embodiment includes enabling, based upon the associating, the nodelay setting upon connection of the request-response communication with the port. Further still, the example embodiment includes sending, in accordance with the enabling, the request-response communication to a destination in communication with the networked computer system. In addition, further example embodiments include configuring the ports on the networked computer system with nodelay values indicating whether a particular port is assigned nodelay or no nodelay for a request portion or request portion of a request-response communication connecting to that particular port.

摘要翻译： 公开了用于网络计算机系统上的响应请求通信的粒度的方法，系统和媒体。 一个示例性实施例包括：由联网计算机系统接收请求 - 响应通信，并且从联网计算机系统上的一组端口将请求响应通信与具有节日设置的端口相关联。 此外，示例性实施例包括在连接请求响应通信与端口时基于关联启用节目设置。 此外，示例实施例包括根据启用的方式向与联网的计算机系统通信的目的地发送请求 - 响应通信。 另外，进一步的示例性实施例包括在网络计算机系统上配置端口，其中节点值指示特定端口是否被分配了节目，或者没有连接到该特定端口的请求响应通信的请求部分或请求部分。

公开(公告)号：US20060037017A1

公开(公告)日：2006-02-16

申请号：US10916985

申请日：2004-08-12

申请人： Jos Accapadi ,  Larry Brenner ,  Andrew Dunshea ,  Dirk Michel

发明人： Jos Accapadi ,  Larry Brenner ,  Andrew Dunshea ,  Dirk Michel

IPC分类号： G06F9/46

CPC分类号： G06F9/5088

摘要： A system, apparatus and method of reducing adverse performance impact due to migration of processes from one processor to another in a multi-processor system are provided. When a process is executing, the number of cycles it takes to fetch each instruction (CPI) of the process is stored. After execution of the process, an average CPI is computed and stored in a storage device that is associated with the process. When a run queue of the multi-processor system is empty, a process may be chosen from the run queue that has the most processes awaiting execution to migrate to the empty run queue. The chosen process is the process that has the highest average number of CPIs.

摘要翻译： 提供了一种在多处理器系统中减少由于处理器从一个处理器迁移到另一个处理器的不利性能影响的系统，装置和方法。 当进程正在执行时，存储获取进程的每个指令（CPI）所需的周期数。 在执行该过程之后，计算平均CPI并将其存储在与该过程相关联的存储设备中。 当多处理器系统的运行队列为空时，可以从运行队列中选择具有等待执行的最多进程迁移到空运行队列的进程。 所选择的过程是具有最高平均CPI值的过程。

公开(公告)号：US20050246461A1

公开(公告)日：2005-11-03

申请号：US10834498

申请日：2004-04-29

申请人： Jos Accapadi ,  Herman Dierks ,  Andrew Dunshea ,  Dirk Michel

发明人： Jos Accapadi ,  Herman Dierks ,  Andrew Dunshea ,  Dirk Michel

IPC分类号： G06F9/48 ,  G06F12/14

CPC分类号： G06F9/4812

摘要： Scheduling threads in a multi-processor computer system including establishing an interrupt threshold for a thread, where the interrupt threshold represents a maximum permissible number of interrupts during thread execution on a processor; executing the thread on a current processor, where the thread has thread affinity for one or more processors including the current processor; counting a number of interrupts during execution of the thread on the current processor; and removing thread affinity for the current processor in dependence upon the counted number of interrupts and the interrupt threshold.

摘要翻译： 在多处理器计算机系统中调度线程，包括建立线程的中断阈值，其中中断阈值表示在处理器上执行线程期间的最大允许中断次数; 在当前处理器上执行线程，其中线程对于包括当前处理器的一个或多个处理器具有线程亲和性; 在当前处理器上的线程执行期间对多个中断进行计数; 并根据计数的中断次数和中断阈值去除当前处理器的线程亲和度。

公开(公告)号：US07337276B2

公开(公告)日：2008-02-26

申请号：US11201642

申请日：2005-08-11

申请人： Jos Accapadi ,  Andrew Dunshea ,  Greg R. Mewhinney ,  Mysore Sathyanaranyana Srinivas

发明人： Jos Accapadi ,  Andrew Dunshea ,  Greg R. Mewhinney ,  Mysore Sathyanaranyana Srinivas

IPC分类号： G06F12/00

CPC分类号： G06F12/0897 ,  G06F12/0891

摘要： A computer implemented method, apparatus, and computer usable code for managing cache data. A partition identifier is associated with a cache entry in a cache, wherein the partition identifier identifies a last partition accessing the cache entry. The partition identifier associated with the cache entry is compared with a previous partition identifier located in a processor register in response to the cache entry being moved into a lower level cache relative to the cache. The cache entry is marked if the partition identifier associated with the cache entry matches the previous partition identifier located in the processor register to form a marked cache entry, wherein the marked cache entry is aged at a slower rate relative to an unmarked cache entry.

摘要翻译： 计算机实现的方法，装置和用于管理高速缓存数据的计算机可用代码。 分区标识符与高速缓存中的高速缓存条目相关联，其中分区标识符标识访问高速缓存条目的最后一个分区。 与高速缓存条目相关联的分区标识符与位于处理器寄存器中的先前分区标识符进行比较，以响应于高速缓存条目相对于高速缓存移动到较低级高速缓存。 如果与高速缓存条目相关联的分区标识与位于处理器寄存器中的先前分区标识符相匹配以形成标记的高速缓存条目，则标记高速缓存条目，其中标记的高速缓存条目相对于未标记的高速缓存条目以较慢的速率进行老化。