公开(公告)号：US20070201216A1

公开(公告)日：2007-08-30

申请号：US10588556

申请日：2004-12-27

申请人： Josef Deuringer ,  Richard Eichhorn ,  Lars Lauer ,  Gerd Morsberger ,  Paul Ponnath ,  Roland Rabe

发明人： Josef Deuringer ,  Richard Eichhorn ,  Lars Lauer ,  Gerd Morsberger ,  Paul Ponnath ,  Roland Rabe

IPC分类号： H05K9/00 ,  H05K1/11

CPC分类号： H01R13/5202 ,  H01J2235/023 ,  H01R12/523 ,  H01R12/58 ,  Y10T29/49126 ,  Y10T29/49165

摘要： A housing comprising a liquid-tight electric bushing is provided. The housing comprises an opening and a printed circuit board comprising at least first and second layers. The first layer is a top side of the printed circuit board and spans the opening. A first contact element is disposed on the top side and in a blind bore through the first layer that extends to the second layer. The second layer is a conductor track in the interior of the printed circuit board.

摘要翻译： 提供了一种包括液密电气套管的壳体。 壳体包括开口和包括至少第一层和第二层的印刷电路板。 第一层是印刷电路板的顶面并跨越开口。 第一接触元件设置在顶侧和盲孔中，穿过延伸到第二层的第一层。 第二层是印刷电路板内部的导体轨迹。

公开(公告)号：US20060140142A1

公开(公告)日：2006-06-29

申请号：US10528604

申请日：2002-09-24

申请人： Ralf Kukla ,  Gerd Morsberger ,  Georg Sporlein ,  Gerhard Goedert ,  Edmund Goetz

发明人： Ralf Kukla ,  Gerd Morsberger ,  Georg Sporlein ,  Gerhard Goedert ,  Edmund Goetz

IPC分类号： H04Q7/00

CPC分类号： H03M13/27 ,  H04L1/0045 ,  H04L1/0071

摘要： A method for processing a bit sequence in a digital communication system, includes the steps of (a) storing the bits of said bit sequence at locations of a memory means indicated by a first interleaving scheme, (b) converting output bit positions into input bit positions according to an inverse of a second interleaving scheme, (c) reading out bits stored at locations of said memory means corresponding to said input bit positions, thereby generating an interleaved sequence which is interleaved according to said first and said second interleaving schemes, and (d) processing said interleaved sequence according to further physical processing steps. Alternatively, step (a) may include storing the bits of said input bit sequence in a memory means and step (b) may include converting output bit positions into input bit positions according to the inverse of a sequential application of a first interleaving scheme and a second interleaving scheme.

摘要翻译： 一种用于处理数字通信系统中的比特序列的方法，包括以下步骤：（a）将所述比特序列的比特存储在由第一交织方案指示的存储器装置的位置处，（b）将输出比特位置转换成输入比特 根据第二交织方案的倒数，（c）读出存储在与所述输入比特位置对应的所述存储装置的位置处的比特，从而产生根据所述第一和所述第二交织方案进行交织的交错序列，以及 （d）根据进一步的物理处理步骤处理所述交错序列。 或者，步骤（a）可以包括将所述输入比特序列的比特存储在存储装置中，并且步骤（b）可以包括根据第一交织方案的顺序应用的反向将输出比特位置转换成输入比特位置 第二交织方案。

公开(公告)号：US20050248473A1

公开(公告)日：2005-11-10

申请号：US10526519

申请日：2002-09-09

申请人： Ralf Kukla ,  Stefan Schutz ,  Georg Sporlein ,  Gerd Morsberger

发明人： Ralf Kukla ,  Stefan Schutz ,  Georg Sporlein ,  Gerd Morsberger

IPC分类号： H03M13/27 ,  H03M13/29 ,  H04L1/00 ,  H03M7/00

CPC分类号： H04L1/0071 ,  H03M13/271 ,  H03M13/2714 ,  H03M13/2764 ,  H03M13/2771 ,  H03M13/2957 ,  H03M13/635

摘要： This invention relates to a method for interleaving, according to an interleaving scheme, an input sequence comprising K bits into an interleaved sequence, comprising the steps of (a) storing the input sequence in a first memory means, (b) generating first indices of N succeeding bits of the interleaved sequence, wherein 1 m(F) N m(F) K, (c) converting, according to an inverse of said interleaving scheme, said first indices into second indices indicative of the positions where said N succeeding bits of the inter-leaved sequence are stored in said first memory means, and (d) reading out said N succeeding bits from said positions in said first memory means, thereby generating at least part of said interleaved sequence.

摘要翻译： 本发明涉及一种根据交织方案将包括K个比特的输入序列交织到交错序列中的方法，包括以下步骤：（a）将输入序列存储在第一存储器装置中，（b）产生第一索引 其中1 m（F）N m（F）K，（c）根据所述交织方案的反向将所述第一索引转换为指示所述N个后续比特的位置的第二索引 并且（d）从所述第一存储器装置中的所述位置读出所述N个后续位，从而产生所述交错序列的至少一部分。

公开(公告)号：US07269149B2

公开(公告)日：2007-09-11

申请号：US10528604

申请日：2002-09-24

申请人： Ralf Kukla ,  Gerd Morsberger ,  Georg Sporlein ,  Gerhard Goedert ,  Edmund Goetz

发明人： Ralf Kukla ,  Gerd Morsberger ,  Georg Sporlein ,  Gerhard Goedert ,  Edmund Goetz

IPC分类号： H04Q7/00

CPC分类号： H03M13/27 ,  H04L1/0045 ,  H04L1/0071

摘要： A method for processing a bit sequence in a digital communication system, includes the steps of (a) storing the bits of said bit sequence at locations of a memory means indicated by a first interleaving scheme, (b) converting output bit positions into input bit positions according to an inverse of a second interleaving scheme, (c) reading out bits stored at locations of said memory means corresponding to said input bit positions, thereby generating an interleaved sequence which is interleaved according to said first and said second interleaving schemes, and (d) processing said interleaved sequence according to further physical processing steps. Alternatively, step (a) may include storing the bits of said input bit sequence in a memory means and step (b) may include converting output bit positions into input bit positions according to the inverse of a sequential application of a first interleaving scheme and a second interleaving scheme.

摘要翻译： 一种用于处理数字通信系统中的比特序列的方法，包括以下步骤：（a）将所述比特序列的比特存储在由第一交织方案指示的存储器装置的位置处，（b）将输出比特位置转换成输入比特 根据第二交织方案的倒数，（c）读出存储在与所述输入比特位置对应的所述存储装置的位置处的比特，从而产生根据所述第一和所述第二交织方案进行交织的交错序列，以及 （d）根据进一步的物理处理步骤处理所述交错序列。 或者，步骤（a）可以包括将所述输入比特序列的比特存储在存储装置中，并且步骤（b）可以包括根据第一交织方案的顺序应用的反向将输出比特位置转换成输入比特位置 第二交织方案。

公开(公告)号：US20050105605A1

公开(公告)日：2005-05-19

申请号：US10500538

申请日：2002-09-18

申请人： Gerd Morsberger ,  Stefan Schutz ,  Georg Sporlein

发明人： Gerd Morsberger ,  Stefan Schutz ,  Georg Sporlein

IPC分类号： H04L1/00 ,  H04L1/08 ,  H04Q1/20

CPC分类号： H04L1/0043 ,  H04L1/0069 ,  H04L1/0071 ,  H04L1/08

摘要： This invention relates to a flexible rate matching method, comprising the steps of: a) receiving a continuous stream of data items at a prespecified rate of a clock signal in a configurable data shift register; b) storing, for each data item stored in the data shirt register, an associated indication of validity in a configurable validity shift register and shifting the indications of validity at said prespecified rate; c) modifying the contents of the data shift register and the validity shift register through puncture/repetition operations so as to achieve a rate matching, and d) outputting valid data items at said prespecified rate using said indications of validity stored in the validity shift register. The invention also relates to a corresponding flexible rate matching apparatus as well as to a computer program product and a processor program product.

摘要翻译： 本发明涉及一种灵活的速率匹配方法，包括以下步骤：a）以可配置数据移位寄存器中的时钟信号的预定速率接收数据项的连续流; b）对于存储在数据移位寄存器中的每个数据项存储可配置的有效性移位寄存器中的有效性的相关指示，并以所述预定速率移位有效性的指示; c）通过穿刺/重复操作来修改数据移位寄存器和有效移位寄存器的内容以便实现速率匹配，以及d）使用存储在有效移位寄存器中的所述有效性指示，以所述预定速率输出有效数据项 。 本发明还涉及相应的灵活速率匹配装置以及计算机程序产品和处理器程序产品。