公开(公告)号：US07185338B2

公开(公告)日：2007-02-27

申请号：US10271838

申请日：2002-10-15

申请人： Joseph Chamdani ,  Yuan Chou

发明人： Joseph Chamdani ,  Yuan Chou

IPC分类号： G06F9/46 ,  G06F9/44

CPC分类号： G06F9/3851 ,  G06F9/30134 ,  G06F9/3838 ,  G06F9/3842

摘要： A computer system includes a processor capable of executing a plurality of N threads of instructions, N being an integer greater than one, with a set of global registers visible to each of the plurality of threads and a plurality of busy bit memory elements used to signal whether or not a register is in use by a thread. The processor includes logic to stall a read from global register if the thread reading the global register is a speculative thread and the busy bits for prior threads are set. The processor might also include a speculative load address memory, into which speculative loads from speculative threads are entered and logic to compare addresses for stores from nonspeculative threads with addressees in the speculative load address memory and invalidate speculative threads corresponding to the speculative load addresses stored in the speculative load address memory. In an efficient implementation, aliasing load instructions can be distinct from nonaliasing load instructions, whereby addresses of aliasing load instructions are selectively stored in the speculative load address memory.

摘要翻译： 计算机系统包括能够执行多个N个指令线程的处理器，N是大于1的整数，其中一组全局寄存器对于多个线程中的每一个可见，以及用于发送信号的多个忙位存储器元件 线程是否使用寄存器。 如果读取全局寄存器的线程是推测线程，并且设置了先前线程的忙位，则处理器包括停止从全局寄存器读取的逻辑。 处理器还可以包括推测性加载地址存储器，其中输入来自推测性线程的推测性负载以及用于比较来自非特定线程的存储器的地址与推测性加载地址存储器中的收件人的逻辑，并使与存储在其中的推测负载地址相对应的推测线程无效 推测负载地址存储器。 在有效的实现中，混叠加载指令可以不同于非加密加载指令，由此将混叠加载指令的地址选择性地存储在推测加载地址存储器中。

公开(公告)号：US20070226722A1

公开(公告)日：2007-09-27

申请号：US11389579

申请日：2006-03-24

申请人： Yuan Chou

发明人： Yuan Chou

IPC分类号： G06F9/45

CPC分类号： G06F8/443 ,  G06F9/44536

摘要： One embodiment of the present invention provides a system that selectively executes different versions of executable code for the same source code. During operation, the system first receives an executable code module which includes two or more versions of executable code for the same source code, wherein the two or more versions of the executable code are optimized in different ways. Next, the system executes the executable code module by first evaluating a test condition, and subsequently executing a specific version of the executable code based on the outcome of the evaluation, so that the execution is optimized for the test condition.

摘要翻译： 本发明的一个实施例提供一种选择性地执行相同源代码的可执行代码的不同版本的系统。 在操作期间，系统首先接收可执行代码模块，该可执行代码模块包括用于相同源代码的可执行代码的两个或多个版本，其中可执行代码的两个或多个版本以不同的方式被优化。 接下来，系统通过首先评估测试条件并随后基于评估结果执行可执行代码的特定版本来执行可执行代码模块，使得针对测试条件优化执行。

公开(公告)号：US20070113022A1

公开(公告)日：2007-05-17

申请号：US11271056

申请日：2005-11-12

申请人： Santosh Abraham ,  Lawrence Spracklen ,  Yuan Chou

发明人： Santosh Abraham ,  Lawrence Spracklen ,  Yuan Chou

IPC分类号： G06F13/28

CPC分类号： G06F12/0859

摘要： Maintaining a cache of indications of exclusively-owned coherence state for memory space units (e.g., cache line) allows reduction, if not elimination, of delay from missing store operations. In addition, the indications are maintained without corresponding data of the memory space unit, thus allowing representation of a large memory space with a relatively small missing store operation accelerator. With the missing store operation accelerator, a store operation, which misses in low-latency memory (e.g., L1 or L2 cache), proceeds as if the targeted memory space unit resides in the low-latency memory, if indicated in the missing store operation accelerator. When a store operation misses in low-latency memory and hits in the accelerator, a positive acknowledgement is transmitted to the writing processing unit allowing the store operation to proceed. An entry is allocated for the store operation, the store data is written into the allocated entry, and the target of the store operation is requested from memory. When a copy of the data at the requested memory space unit returns, the rest of the allocated entry is updated.

摘要翻译： 维护用于存储器空间单元（例如，高速缓存行）的专有相干状态的指示的缓存允许减少（如果不是消除）缺失存储操作的延迟。 此外，在没有存储器空间单元的相应数据的情况下维持指示，从而允许用相对较小的缺少存储操作加速器来表示大的存储空间。 在缺少存储操作加速器的情况下，在低延迟存储器（例如L1或L2高速缓存）中丢失的存储操作如同目标存储器空间单元驻留在低延迟存储器中那样进行，如果在缺少的存储操作 加速器。 当存储操作在低延迟存储器中错过并且在加速器中点击时，肯定确认被发送到写入处理单元，从而允许存储操作继续进行。 为存储操作分配条目，将存储数据写入分配的条目，并且从存储器请求存储操作的目标。 当所请求的存储器空间单元上的数据的副本返回时，所分配的条目的其余部分被更新。