公开(公告)号：US08438207B2

公开(公告)日：2013-05-07

申请号：US11864580

申请日：2007-09-28

申请人： Josephine Ammer Bolotski ,  Jenny Bui ,  Qi Lu

发明人： Josephine Ammer Bolotski ,  Jenny Bui ,  Qi Lu

IPC分类号： G06F7/52

CPC分类号： G06G7/16 ,  G06F17/10 ,  H03H17/0223 ,  H03H17/06

摘要： Two process-tolerant arithmetic circuit architectures are implemented to develop functional blocks for error-tolerant applications such as FIR filters and FFT blocks. The resulting blocks may achieve computational performance of up to 42 times higher than conventional architectures. Embodiments adaptively change the precision of the computation to achieve a high precision computation given the underlying speed of the circuit. The resulting improvement can be allocated to increasing yield or dynamically trading off between reduced power consumption, faster computation, or higher-fidelity computation.

摘要翻译： 实现两个容错算术电路架构来开发诸如FIR滤波器和FFT块之类的容错应用的功能块。 所得到的块可以实现高达传统架构的42倍的计算性能。 给定电路的底层速度，实施方式自适应地改变计算的精度以实现高精度计算。 所得到的改进可以被分配用于在降低的功率消耗，更快的计算或更高保真度的计算之间提高产量或动态地折中。

公开(公告)号：US20130246497A1

公开(公告)日：2013-09-19

申请号：US13888276

申请日：2013-05-06

申请人： Josephine Ammer Bolotski ,  Jenny Bui ,  Qi Lu

发明人： Josephine Ammer Bolotski ,  Jenny Bui ,  Qi Lu

IPC分类号： G06G7/16

CPC分类号： G06G7/16 ,  G06F17/10 ,  H03H17/0223 ,  H03H17/06

摘要： Two process-tolerant arithmetic circuit architectures are implemented to develop functional blocks for error-tolerant applications such as FIR filters and FFT blocks. The resulting blocks may achieve computational performance of up to 42 times higher than conventional architectures. Embodiments adaptively change the precision of the computation to achieve a high precision computation given the underlying speed of the circuit. The resulting improvement can be allocated to increasing yield or dynamically trading off between reduced power consumption, faster computation, or higher-fidelity computation.

公开(公告)号：US20090089348A1

公开(公告)日：2009-04-02

申请号：US11864580

申请日：2007-09-28

申请人： Josephine Ammer Bolotski ,  Jenny Bui ,  Qi Lu

发明人： Josephine Ammer Bolotski ,  Jenny Bui ,  Qi Lu

IPC分类号： G06F17/10

CPC分类号： G06G7/16 ,  G06F17/10 ,  H03H17/0223 ,  H03H17/06

摘要： Two process-tolerant arithmetic circuit architectures are implemented to develop functional blocks for error-tolerant applications such as FIR filters and FFT blocks. The resulting blocks may achieve computational performance of up to 42 times higher than conventional architectures. Embodiments adaptively change the precision of the computation to achieve a high precision computation given the underlying speed of the circuit. The resulting improvement can be allocated to increasing yield or dynamically trading off between reduced power consumption, faster computation, or higher-fidelity computation.

摘要翻译： 实现两个容错算术电路架构来开发诸如FIR滤波器和FFT块之类的容错应用的功能块。 所得到的块可以实现高达传统架构的42倍的计算性能。 给定电路的底层速度，实施方式自适应地改变计算的精度以实现高精度计算。 所得到的改进可以被分配用于在降低的功率消耗，更快的计算或更高保真度的计算之间提高产量或动态地折中。