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1.发明授权Delegating network processor operations to star topology serial bus interfaces 失效将网络处理器操作委托给星形拓扑串行总线接口公开(公告)号：US08065456B2
公开(公告)日：2011-11-22
申请号：US12019576
申请日：2008-01-24
申请人： Julianne Jiang Zhu , David T. Hass
发明人： Julianne Jiang Zhu , David T. Hass
CPC分类号： G06F13/4286 , G06F9/3851 , G06F9/3857 , G06F9/3867 , G06F12/0813 , H04L49/109
摘要： An advanced processor comprises a plurality of multithreaded processor cores configured to support a plurality of software generated read or write instructions for interfacing with a star topology serial bus interface. The multiple-core processor has at least one of an internal fast messaging network or an interface switch interconnect configured to link the processor cores together such that each processor core has a data pathway to each of the other processor cores without going through memory. The fast messaging network or interface switch is also configured to be operably coupled to the star topology serial bus interface. In one aspect of an embodiment of the invention, the fast messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes.
摘要翻译： 高级处理器包括多个多线程处理器核，其被配置为支持多个软件产生的读取或写入指令，用于与星形拓扑串行总线接口进行接口。 多核处理器具有内部快速消息传递网络或配置成将处理器核心链接在一起的接口交换机互连中的至少一个，使得每个处理器核心具有到每个其他处理器核心的数据通路，而不经过存储器。 快速消息传递网络或接口交换机也被配置为可操作地耦合到星形拓扑串行总线接口。 在本发明的实施例的一个方面，快速消息传递网络连接到能够支持多个高带宽PCIe通道的高带宽星形拓扑串行总线，例如PCI Express（PCIe）接口。
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2.发明授权Delegating network processor operations to star topology serial bus interfaces 失效将网络处理器操作委托给星形拓扑串行总线接口公开(公告)号：US08543747B2
公开(公告)日：2013-09-24
申请号：US13253044
申请日：2011-10-04
申请人： Julianne Jiang Zhu , David T. Hass
发明人： Julianne Jiang Zhu , David T. Hass
CPC分类号： G06F13/4286 , G06F9/3851 , G06F9/3857 , G06F9/3867 , G06F12/0813 , H04L49/109
摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. The data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. In one aspect of an embodiment of the invention, the messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
摘要翻译： 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 数据交换机互连通过其相应的数据高速缓存耦合到每个处理器核心，并且消息传递网络通过其各自的消息站耦合到每个处理器核心。 在本发明的实施例的一个方面，消息传递网络连接到能够支持多个高带宽PCIe通道的高带宽星形拓扑串行总线，例如PCI Express（PCIe）接口。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。
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3.发明申请DELEGATING NETWORK PROCESSOR OPERATIONS TO STAR TOPOLOGY SERIAL BUS INTERFACES 失效删除网络处理器操作到星形拓扑串行总线接口公开(公告)号：US20120089762A1
公开(公告)日：2012-04-12
申请号：US13253044
申请日：2011-10-04
申请人： Julianne Jiang Zhu , David T. Hass
发明人： Julianne Jiang Zhu , David T. Hass
IPC分类号： G06F13/14
CPC分类号： G06F13/4286 , G06F9/3851 , G06F9/3857 , G06F9/3867 , G06F12/0813 , H04L49/109
摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. The data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. In one aspect of an embodiment of the invention, the messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
摘要翻译： 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 数据交换机互连通过其相应的数据高速缓存耦合到每个处理器核心，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 在本发明的实施例的一个方面，消息传递网络连接到能够支持多个高带宽PCIe通道的高带宽星形拓扑串行总线，例如PCI Express（PCIe）接口。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。
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4.发明授权Delegating network processor operations to star topology serial bus interfaces 有权将网络处理器操作委托给星形拓扑串行总线接口公开(公告)号：US08037224B2
公开(公告)日：2011-10-11
申请号：US11831887
申请日：2007-07-31
申请人： Julianne Jiang Zhu , David T. Hass
发明人： Julianne Jiang Zhu , David T. Hass
CPC分类号： G06F13/4286 , G06F9/3851 , G06F9/3857 , G06F9/3867 , G06F12/0813 , H04L49/109
摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. The data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. In one aspect of an embodiment of the invention, the messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
摘要翻译： 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 数据交换机互连通过其相应的数据高速缓存耦合到每个处理器核心，并且消息传递网络通过其各自的消息站耦合到每个处理器核心。 在本发明的实施例的一个方面，消息传递网络连接到能够支持多个高带宽PCIe通道的高带宽星形拓扑串行总线，例如PCI Express（PCIe）接口。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。
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5.发明申请DELEGATING NETWORK PROCESSOR OPERATIONS TO STAR TOPOLOGY SERIAL BUS INTERFACES 审中-公开删除网络处理器操作到星形拓扑串行总线接口公开(公告)号：US20100318703A1
公开(公告)日：2010-12-16
申请号：US12815092
申请日：2010-06-14
申请人： Julianne Jiang Zhu , David T. Hass
发明人： Julianne Jiang Zhu , David T. Hass
CPC分类号： G06F13/4286 , G06F9/3851 , G06F9/3857 , G06F9/3867 , G06F12/0813 , H04L49/109
摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. The data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. In one aspect of an embodiment of the invention, the messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
摘要翻译： 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 数据交换机互连通过其相应的数据高速缓存耦合到每个处理器核心，并且消息传递网络通过其各自的消息站耦合到每个处理器核心。 在本发明的实施例的一个方面，消息传递网络连接到能够支持多个高带宽PCIe通道的高带宽星形拓扑串行总线，例如PCI Express（PCIe）接口。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。
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6.发明申请DELEGATING NETWORK PROCESSOR OPERATIONS TO STAR TOPOLOGY SERIAL BUS INTERFACES 失效删除网络处理器操作到星形拓扑串行总线接口公开(公告)号：US20080184008A1
公开(公告)日：2008-07-31
申请号：US12019576
申请日：2008-01-24
申请人： Julianne Jiang Zhu , David T. Hass
发明人： Julianne Jiang Zhu , David T. Hass
CPC分类号： G06F13/4286 , G06F9/3851 , G06F9/3857 , G06F9/3867 , G06F12/0813 , H04L49/109
摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging net work is coupled to each of the processor cores and a plurality of communication ports. The data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. In one aspect of an embodiment of the invention, the messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
摘要翻译： 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息网络工作耦合到每个处理器核和多个通信端口。 数据交换机互连通过其相应的数据高速缓存耦合到每个处理器核心，并且消息传递网络通过其各自的消息站耦合到每个处理器核心。 在本发明的实施例的一个方面，消息传递网络连接到能够支持多个高带宽PCIe通道的高带宽星形拓扑串行总线，例如PCI Express（PCIe）接口。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。
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