公开(公告)号：US08671395B1

公开(公告)日：2014-03-11

申请号：US12879458

申请日：2010-09-10

申请人： Jun Yuan ,  Akok Jain ,  Manpreet Singh Reehal ,  Vinaya Kumar Singh

发明人： Jun Yuan ,  Akok Jain ,  Manpreet Singh Reehal ,  Vinaya Kumar Singh

IPC分类号： G06F9/44 ,  G06F9/455

CPC分类号： G06F17/5009 ,  G06F2217/06

摘要： The present disclosure relates to a method for avoiding deadends in a constrained simulation. The method may include analyzing a first deadend during a simulation and a first constraint of the simulation. The method may further include determining if the first constraint causes the first deadend. If the first constraint causes the first deadend, the method may also include defining a first lookahead constraint corresponding to the first constraint. The method may additionally include rerunning a first previous cycle in the simulation while adding the first lookahead constraint to the simulation.

摘要翻译： 本公开涉及一种用于在受限模拟中避免死角的方法。 该方法可以包括在模拟期间分析第一死区和模拟的第一约束。 所述方法还可以包括确定所述第一约束是否引起所述第一死锁。 如果第一约束导致第一个停止，则该方法还可以包括定义与第一约束相对应的第一前瞻约束。 该方法可以另外包括在模拟中重新运行第一先前循环，同时将第一前视约束添加到模拟中。

公开(公告)号：US07810056B1

公开(公告)日：2010-10-05

申请号：US11711950

申请日：2007-02-27

申请人： Tarun Garg ,  Vinaya Kumar Singh

发明人： Tarun Garg ,  Vinaya Kumar Singh

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A method and system for implementing context aware synthesis of assertions is disclosed. The method and system for assertion synthesis includes converting an assertion formula to sequence implication form using semantic preserving rewrite rules, performing optimizations on the resulting formula to reduce the number of state-bits in a final FSM (Finite State Machine), and synthesizing the resulting formula to the final FSM using context aware sequence synthesis.

摘要翻译： 公开了用于实现上下文感知合成的断言的方法和系统。 用于断言合成的方法和系统包括使用语义保留重写规则将断言公式转换为序列暗示形式，对所得公式执行优化以减少最终FSM（有限状态机）中的状态位数，并且合成所得到的 公式到最终的FSM使用上下文感知序列合成。

公开(公告)号：US08104001B2

公开(公告)日：2012-01-24

申请号：US12263372

申请日：2008-10-31

申请人： Amir Lehavot ,  Vinaya Kumar Singh ,  Joezac John Zachariah ,  Jose Barandiaran ,  Axel Siegfried Scherer

发明人： Amir Lehavot ,  Vinaya Kumar Singh ,  Joezac John Zachariah ,  Jose Barandiaran ,  Axel Siegfried Scherer

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5081

摘要： An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described.

摘要翻译： 描述了一种用于过约束电路验证环境的自动调试方法和系统。 收集和提供与电路评估和/或过度约束事件相关的有用信息。 该信息可以包括：发生过度约束事件的时钟周期; 识别将导致过度约束事件发生的约束的最小子集; 信号端口具有不能在不同信号状态之间切换的相关信号; 在评估期间是否发生触发信号事件; 指示评估中的约束是否可实现等。还描述了用于检测和获得有用信息的新方法。

公开(公告)号：US08099695B1

公开(公告)日：2012-01-17

申请号：US11498472

申请日：2006-08-02

申请人： Amir Lehavot ,  Vinaya Kumar Singh ,  Joezac John Zachariah ,  Jose Barandiaran ,  Axel Siegfried Scherer

发明人： Amir Lehavot ,  Vinaya Kumar Singh ,  Joezac John Zachariah ,  Jose Barandiaran ,  Axel Siegfried Scherer

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5081

摘要： An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described.

摘要翻译： 描述了一种用于过约束电路验证环境的自动调试方法和系统。 收集和提供与电路评估和/或过度约束事件相关的有用信息。 该信息可以包括：发生过度约束事件的时钟周期; 识别将导致过度约束事件发生的约束的最小子集; 信号端口具有不能在不同信号状态之间切换的相关信号; 在评估期间是否发生触发信号事件; 指示评估中的约束是否可实现等。还描述了用于检测和获得有用信息的新方法。

公开(公告)号：US20090144680A1

公开(公告)日：2009-06-04

申请号：US12263351

申请日：2008-10-31

申请人： Amir LEHAVOT ,  Vinaya Kumar Singh ,  Joezac John Zachariah ,  Jose Barandiaran ,  Axel Siegfried Scherer

发明人： Amir LEHAVOT ,  Vinaya Kumar Singh ,  Joezac John Zachariah ,  Jose Barandiaran ,  Axel Siegfried Scherer

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described.

公开(公告)号：US08099696B2

公开(公告)日：2012-01-17

申请号：US12263377

申请日：2008-10-31

申请人： Amir Lehavot ,  Vinaya Kumar Singh ,  Joezac John Zachariah ,  Jose Barandiaran ,  Axel Siegfried Scherer

发明人： Amir Lehavot ,  Vinaya Kumar Singh ,  Joezac John Zachariah ,  Jose Barandiaran ,  Axel Siegfried Scherer

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5081

摘要： An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described.

摘要翻译： 描述了一种用于过约束电路验证环境的自动调试方法和系统。 收集和提供与电路评估和/或过度约束事件相关的有用信息。 该信息可以包括：发生过度约束事件的时钟周期; 识别将导致过度约束事件发生的约束的最小子集; 信号端口具有不能在不同信号状态之间切换的相关信号; 在评估期间是否发生触发信号事件; 指示评估中的约束是否可实现等。还描述了用于检测和获得有用信息的新方法。

公开(公告)号：US07428712B1

公开(公告)日：2008-09-23

申请号：US11281426

申请日：2005-11-18

申请人： Vinaya Kumar Singh ,  Ravi Prakash ,  Alok Jain ,  Kavita Ravi

发明人： Vinaya Kumar Singh ,  Ravi Prakash ,  Alok Jain ,  Kavita Ravi

IPC分类号： G06F17/50

CPC分类号： G06F17/504

摘要： Aspects of computing design invariants, by using approximate reachability analysis, include reducing the circuit model for verification and synthesis. Further included is computing invariants using approximate reachability analysis to optimize a circuit model by identifying a plurality of next states for a present state, the plurality of next states capable of being reached from the present state in one transition. The plurality of bits of the next states are compared with a plurality of bits of the present state, and each bit of the present state that is different from at least one next state is changed to variant.

摘要翻译： 计算设计不变量的方面，通过使用近似可达性分析，包括减少验证和综合的电路模型。 还包括使用近似可达性分析的计算不变量，以通过识别当前状态的多个下一状态来优化电路模型，该多个下一状态能够在一个转换中从当前状态到达。 将下一个状态的多个比特与当前状态的多个比特进行比较，并且与至少一个下一个状态不同的当前状态的每个比特被改变为变体。

公开(公告)号：US07984401B2

公开(公告)日：2011-07-19

申请号：US12263351

申请日：2008-10-31

申请人： Amir Lehavot ,  Vinaya Kumar Singh ,  Joezac John Zachariah ,  Jose Barandiaran ,  Axel Siegfried Scherer

发明人： Amir Lehavot ,  Vinaya Kumar Singh ,  Joezac John Zachariah ,  Jose Barandiaran ,  Axel Siegfried Scherer

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5081

摘要： An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described.

摘要翻译： 描述了一种用于过约束电路验证环境的自动调试方法和系统。 收集和提供与电路评估和/或过度约束事件相关的有用信息。 该信息可以包括：发生过度约束事件的时钟周期; 识别将导致过度约束事件发生的约束的最小子集; 信号端口具有不能在不同信号状态之间切换的相关信号; 在评估期间是否发生触发信号事件; 指示评估中的约束是否可实现等。还描述了用于检测和获得有用信息的新方法。

公开(公告)号：US07712060B1

公开(公告)日：2010-05-04

申请号：US11712003

申请日：2007-02-27

申请人： Tarun Garg ,  Vinaya Kumar Singh ,  Pratik Mahajan ,  Mohamad Shaved

发明人： Tarun Garg ,  Vinaya Kumar Singh ,  Pratik Mahajan ,  Mohamad Shaved

IPC分类号： G06F17/50

CPC分类号： G06F17/504

摘要： A method and system for handling assertion libraries in verification of a design are disclosed. The method and system include structuring and implementing at least one verification component in at least one of the assertion libraries with at least one standard assertion language supported by at least one verification tool, creating an assertion library element for a specific requirement for verification of the design without dependence on the at least one verification tool for the assertion library element, and resolving assertion status. With the disclosed method and system, visualization of assertion status at various levels of design hierarchy and at verification component level may be achieved, and implementing verification techniques may include optimization techniques during and/or after verification.

摘要翻译： 公开了一种在设计验证中处理断言库的方法和系统。 该方法和系统包括在至少一个断言库中的至少一个断言库中构建并实现由至少一个验证工具所支持的至少一个标准断言语言来创建用于验证设计的特定要求的断言库元素 而不依赖于断言库元件的至少一个验证工具，并且解析断言状态。 利用所公开的方法和系统，可以实现设计层级和验证组件级别的各种级别的断言状态的可视化，并且实现验证技术可以包括验证期间和/或之后的优化技术。

公开(公告)号：US20090144683A1

公开(公告)日：2009-06-04

申请号：US12263372

申请日：2008-10-31

申请人： Amir Lehavot ,  Vinaya Kumar Singh ,  Joezac John Zachariah ,  Jose Barandiaran ,  Axel Siegfried Scherer

发明人： Amir Lehavot ,  Vinaya Kumar Singh ,  Joezac John Zachariah ,  Jose Barandiaran ,  Axel Siegfried Scherer

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described.