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1.发明申请Power semiconductor device having buried gate bus and process for fabricating the same 审中-公开具有掩埋栅极总线的功率半导体器件及其制造方法公开(公告)号：US20060216895A1
公开(公告)日：2006-09-28
申请号：US11165077
申请日：2005-06-23
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L21/76838 , H01L29/66348 , H01L29/66621 , H01L29/7834
摘要： A power semiconductor device includes a substrate, a gate oxide layer, a gate bus layer, an inter-layer dielectric layer and a metal bus layer. The substrate has a trench structure therein. The gate oxide layer is formed on surfaces of the substrate and the trench structure. The gate bus layer is formed on the gate oxide layer inside the trench structure. The inter-layer dielectric layer is formed on the gate oxide layer and a portion of the gate bus layer, thereby defining a contact window. The metal bus layer is formed on the inter-layer dielectric layer and the trench structure, and connected to the gate bus layer via the contact window.
摘要翻译： 功率半导体器件包括衬底，栅极氧化物层，栅极总线层，层间电介质层和金属母线层。 衬底在其中具有沟槽结构。 栅极氧化层形成在衬底和沟槽结构的表面上。 栅极总线层形成在沟槽结构内部的栅极氧化物层上。 层间电介质层形成在栅极氧化物层和栅极总线层的一部分上，由此限定接触窗口。 金属总线层形成在层间电介质层和沟槽结构上，并通过接触窗口连接到栅极总线层。
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2.发明申请公开(公告)号：US20060255374A1
公开(公告)日：2006-11-16
申请号：US11194354
申请日：2005-08-01
IPC分类号： H01L29/80
CPC分类号： H01L29/42316 , H01L23/482 , H01L29/0619 , H01L29/1066 , H01L29/66901 , H01L29/8083 , H01L2924/0002 , H01L2924/00
摘要： A manufacturing process and a power junction field-effect transistor (JFET) are provided. The basic concept of the present invention is to allow the current to flow vertically from the drain region on the bottom side to the source region on the topside of the device. By regulating the voltage applied between the gate regions and the source region, the power junction field-effect transistor (JFET) of the present invention can be built to handle large current and higher voltage for power management purposes, as is similar to the metal oxide semiconductor field effect transistor (MOSFET).
摘要翻译： 提供制造工艺和功率结场效应晶体管（JFET）。 本发明的基本概念是允许电流从底侧的漏极区域到器件的顶侧上的源极区域垂直流动。 通过调节施加在栅极区域和源极区域之间的电压，可以构建本发明的功率结场效应晶体管（JFET），以处理用于电力管理目的的大电流和较高电压，类似于金属氧化物 半导体场效应晶体管（MOSFET）。
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3.发明授权公开(公告)号：US07214601B2
公开(公告)日：2007-05-08
申请号：US11194354
申请日：2005-08-01
IPC分类号： H01L21/20
CPC分类号： H01L29/42316 , H01L23/482 , H01L29/0619 , H01L29/1066 , H01L29/66901 , H01L29/8083 , H01L2924/0002 , H01L2924/00
摘要： A manufacturing process and a power junction field-effect transistor (JFET) are provided. The basic concept of the present invention is to allow the current to flow vertically from the drain region on the bottom side to the source region on the topside of the device. By regulating the voltage applied between the gate regions and the source region, the power junction field-effect transistor (JFET) of the present invention can be built to handle large current and higher voltage for power management purposes, as is similar to the metal oxide semiconductor field effect transistor (MOSFET).
摘要翻译： 提供制造工艺和功率结场效应晶体管（JFET）。 本发明的基本概念是允许电流从底侧的漏极区域到器件的顶侧上的源极区域垂直流动。 通过调节施加在栅极区域和源极区域之间的电压，可以构建本发明的功率结场效应晶体管（JFET），以处理用于电力管理目的的大电流和较高电压，类似于金属氧化物 半导体场效应晶体管（MOSFET）。
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公开(公告)号：US20060270132A1
公开(公告)日：2006-11-30
申请号：US11194847
申请日：2005-08-01
IPC分类号： H01L21/337
CPC分类号： H01L29/8083 , H01L29/1066
摘要： A manufacturing process and a power junction field-effect transistor (JFET) are provided. The basic concept of the present invention is to allow the current to flow vertically from the drain region on the bottom side to the source region on the topside of the device. By regulating the voltage applied between the gate regions and the source region, the power junction field-effect transistor (JFET) of the present invention can be built to handle large current and higher voltage for power management purposes, as is similar to the metal oxide semiconductor field effect transistor (MOSFET).
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公开(公告)号：US20060237782A1
公开(公告)日：2006-10-26
申请号：US11194353
申请日：2005-08-01
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/0869 , H01L29/1095
摘要： A power semiconductor device includes a substrate, a well region, a body region, a trench gate, a gate oxide layer, an L-shaped source region, an inter-layer dielectric layer and a metal layer. The body region is formed on the well region. The trench gate is formed at bilateral sides of the well region. The gate oxide layer is formed on sidewall and bottom of the trench gate. The L-shaped source region has a horizontal portion and a vertical portion formed on a portion of top region and bilateral sides of the body region, respectively. The inter-layer dielectric layer is formed on the trench gate and a portion of the L-shaped source region, thereby defining a contact window therein. The metal layer is formed on the inter-layer dielectric layer, the body region and the L-shaped source region, and connected to the L-shaped source region via the contact window.
摘要翻译： 功率半导体器件包括衬底，阱区，体区，沟槽栅，栅极氧化层，L形源极区，层间电介质层和金属层。 身体区域形成在井区域上。 沟槽门形成在井区的双侧。 栅极氧化层形成在沟槽栅极的侧壁和底部。 L形源区域具有分别形成在身体区域的顶部区域和双侧的一部分上的水平部分和垂直部分。 层间电介质层形成在沟槽栅极和L形源极区域的一部分上，由此在其中限定接触窗口。 金属层形成在层间电介质层，主体区域和L形源极区域上，并且经由接触窗口连接到L形源极区域。
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