公开(公告)号：US20130069236A1

公开(公告)日：2013-03-21

申请号：US13238294

申请日：2011-09-21

申请人： Jung-Hsuan Chen ,  May Chang ,  Chiting Cheng ,  Li-Chun Tien

发明人： Jung-Hsuan Chen ,  May Chang ,  Chiting Cheng ,  Li-Chun Tien

IPC分类号： H01L23/52 ,  G06F17/50

CPC分类号： H01L27/0207 ,  H01L2027/11859

摘要： Provided are semiconductor device cells, methods for forming the semiconductor device cells and a layout style for the semiconductor device cells. The device cells may be repetitive cells used throughout an integrated circuit. The layout style utilizes an area at the polysilicon level that is void of polysilicon and which can accommodate conductive leads therein or thereover. The conductive leads are formed of material typically used for contacts or vias and are disposed beneath the first metal interconnect level which couples device cells to one another. The subjacent local conductive leads may form subjacent signal lines allowing for additional power mesh lines to be included within the limited number of metal tracks that can be accommodated within a device cell and in accordance with metal track design spacing rules.

摘要翻译： 提供半导体器件单元，用于形成半导体器件单元的方法和用于半导体器件单元的布局样式。 器件单元可以是整个集成电路中使用的重复单元。 布局样式利用多晶硅级别的无多晶硅的区域，并且其可以容纳其中或其中的导电引线。 导电引线由通常用于触点或通孔的材料形成，并且设置在将器件单元彼此耦合的第一金属互连级之下。 下面的局部导电引线可以形成下面的信号线，允许额外的功率网线被包括在可以容纳在器件单元内并根据金属轨道设计间隔规则的有限数量的金属轨道内。

公开(公告)号：US08816403B2

公开(公告)日：2014-08-26

申请号：US13238294

申请日：2011-09-21

申请人： Jung-Hsuan Chen ,  May Chang ,  Chiting Cheng ,  Li-Chun Tien

发明人： Jung-Hsuan Chen ,  May Chang ,  Chiting Cheng ,  Li-Chun Tien

IPC分类号： H01L27/118 ,  H01L23/522

CPC分类号： H01L27/0207 ,  H01L2027/11859

摘要： Provided are semiconductor device cells, methods for forming the semiconductor device cells and a layout style for the semiconductor device cells. The device cells may be repetitive cells used throughout an integrated circuit. The layout style utilizes an area at the polysilicon level that is void of polysilicon and which can accommodate conductive leads therein or thereover. The conductive leads are formed of material typically used for contacts or vias and are disposed beneath the first metal interconnect level which couples device cells to one another. The subjacent local conductive leads may form subjacent signal lines allowing for additional power mesh lines to be included within the limited number of metal tracks that can be accommodated within a device cell and in accordance with metal track design spacing rules.

摘要翻译： 提供半导体器件单元，用于形成半导体器件单元的方法和用于半导体器件单元的布局样式。 器件单元可以是整个集成电路中使用的重复单元。 布局样式利用多晶硅级别的无多晶硅的区域，并且可以容纳其中或其中的导电引线。 导电引线由通常用于触点或通孔的材料形成，并且设置在将器件单元彼此耦合的第一金属互连级之下。 下面的局部导电引线可以形成下面的信号线，允许额外的功率网线包括在可以容纳在器件单元内并根据金属轨道设计间隔规则的有限数量的金属轨道内。