公开(公告)号：US20080280390A1

公开(公告)日：2008-11-13

申请号：US12045612

申请日：2008-03-10

申请人： Jung-In KIM ,  Jae-Hee OH ,  Jun-Hyok KONG ,  Jae-Hyun PARK ,  Kwang-Woo LEE

发明人： Jung-In KIM ,  Jae-Hee OH ,  Jun-Hyok KONG ,  Jae-Hyun PARK ,  Kwang-Woo LEE

IPC分类号： H01L47/00

CPC分类号： H01L27/2409 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/141 ,  H01L45/1683

摘要： A method of fabricating a semiconductor memory device having a self-aligned electrode is provided. An interlayer insulating layer having a contact hole is formed on a substrate. A phase change pattern partially filling the contact hole is formed. A bit line which includes a bit extension self-aligned to the phase change pattern and crosses over the interlayer insulating layer is formed. The bit extension may extend in the contact hole on the phase change pattern. The bit extension contacts the phase change pattern.

摘要翻译： 提供了一种制造具有自对准电极的半导体存储器件的方法。 在基板上形成具有接触孔的层间绝缘层。 形成部分填充接触孔的相变图案。 形成了包括与相变图案自对准并与层间绝缘层交叉的位扩展的位线。 钻头延伸部可以在相变图案上的接触孔中延伸。 位扩展接触相变模式。

公开(公告)号：US20080203455A1

公开(公告)日：2008-08-28

申请号：US12034482

申请日：2008-02-20

申请人： Sung-Ho JANG ,  Yong-Jin CHOI ,  Min-Sung KANG ,  Kwang-Woo LEE

发明人： Sung-Ho JANG ,  Yong-Jin CHOI ,  Min-Sung KANG ,  Kwang-Woo LEE

IPC分类号： H01L27/108 ,  H01L21/28

CPC分类号： H01L29/66553 ,  H01L27/10814 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66621

摘要： A semiconductor device employing a transistor having a recessed channel region and a method of fabricating the same is disclosed. A semiconductor substrate has an active region. A trench structure is defined within the active region. The trench structure includes an upper trench region adjacent to a surface of the active region, a lower trench region and a buffer trench region interposed between the upper trench region and the lower trench region. A width of the lower trench region may be greater than a width of the upper trench region. An inner wall of the trench structure may include a convex region interposed between the upper trench region and the buffer trench region and another convex region interposed between the buffer trench region and the lower trench region. A gate electrode is disposed in the trench structure. A gate dielectric layer is interposed between the gate electrode and the trench structure.

摘要翻译： 公开了采用具有凹陷沟道区的晶体管的半导体器件及其制造方法。 半导体衬底具有有源区。 沟槽结构被限定在有源区域内。 沟槽结构包括与有源区的表面相邻的上沟槽区，下沟槽区和介于上沟槽区和下沟槽区之间的缓冲沟槽区。 下沟槽区域的宽度可以大于上沟槽区域的宽度。 沟槽结构的内壁可以包括插入在上沟槽区域和缓冲沟槽区域之间的凸起区域和插入在缓冲沟槽区域和下部沟槽区域之间的另一个凸起区域。 栅电极设置在沟槽结构中。 栅电介质层介于栅电极和沟槽结构之间。