公开(公告)号：US20060224841A1

公开(公告)日：2006-10-05

申请号：US11388972

申请日：2006-03-27

申请人： Junichi Terai ,  Yasunori Yamamoto ,  Keizo Sumida ,  Yoshiteru Mino ,  Yoshinori Tokimoto

发明人： Junichi Terai ,  Yasunori Yamamoto ,  Keizo Sumida ,  Yoshiteru Mino ,  Yoshinori Tokimoto

IPC分类号： G06F13/00

CPC分类号： G06F9/4403

摘要： An information processing device is provided in which a valid initial program is transferred to a RAM while avoiding a invalid block which is present in a low reliable storage device, such as a NAND-type flash memory or the like. A management information storing section 29 stores management information 30 indicating a position of a invalid block in a first storage device 31. When an information processing device 1 is powered on, a transfer determination section 20 is controlled to read a BSP 26 from a valid block of a first storage device 11 based on the management information 30, and transfer the BSP 26 to a second storage device 32. Thereby, it is possible to avoid reading of a invalid block present in the first storage device 31.

公开(公告)号：US07543137B2

公开(公告)日：2009-06-02

申请号：US11388972

申请日：2006-03-27

申请人： Junichi Terai ,  Yasunori Yamamoto ,  Keizo Sumida ,  Yoshiteru Mino ,  Yoshinori Tokimoto

发明人： Junichi Terai ,  Yasunori Yamamoto ,  Keizo Sumida ,  Yoshiteru Mino ,  Yoshinori Tokimoto

IPC分类号： G06F9/00 ,  G06F9/24 ,  G06F13/00

CPC分类号： G06F9/4403

摘要： An information processing device is provided in which a valid initial program is transferred to a RAM while avoiding a invalid block which is present in a low reliable storage device, such as a NAND-type flash memory or the like. A management information storing section 29 stores management information 30 indicating a position of a invalid block in a first storage device 31. When an information processing device 1 is powered on, a transfer determination section 20 is controlled to read a BSP 26 from a valid block of a first storage device 11 based on the management information 30, and transfer the BSP 26 to a second storage device 32. Thereby, it is possible to avoid reading of a invalid block present in the first storage device 31.

摘要翻译： 提供一种信息处理装置，其中有效的初始程序被传送到RAM，同时避免存在于诸如NAND型闪存等的低可靠性存储装置中的无效块。 管理信息存储部分29将指示无效块的位置的管理信息30存储在第一存储装置31中。当信息处理装置1通电时，传送确定部分20被控制以从有效块读取BSP 26 基于管理信息30的第一存储装置11，并将BSP 26传送到第二存储装置32.由此，可以避免读取第一存储装置31中存在的无效块。

公开(公告)号：US07925928B2

公开(公告)日：2011-04-12

申请号：US11984008

申请日：2007-11-13

申请人： Yasunori Yamamoto ,  Keizo Sumida ,  Yoshiteru Mino

发明人： Yasunori Yamamoto ,  Keizo Sumida ,  Yoshiteru Mino

IPC分类号： G06F11/00

CPC分类号： G06F11/1417 ,  G06F11/1004

摘要： After power activation, a transferer 14 detects a bootstrap program 111 having a first error check code 114 assigned thereto and being stored in a first storage device 11, subjects the bootstrap program 111 to an error detection/correction process, and transfers the bootstrap program 111 to the second storage device 12. If the transfer is properly completed, by executing the bootstrap program 111 on the second storage device 12, the CPU 10 performs an error detection/correction process for a main program 112 having a second error check code 115 assigned thereto, and transfers the main program 112 to a third storage device 13, after which the CPU's control branches out to the main program 112 on the third storage device 13. As a result, system boot can be performed without employing a NOR type flash memory.

摘要翻译： 在电源激活之后，传送器14检测具有分配给其的第一错误检查码114并被存储在第一存储装置11中的自举程序111，使自举程序111进行错误检测/校正处理，并且传送引导程序111 如果传送正确完成，则通过在第二存储装置12上执行自举程序111，CPU 10对分配了第二错误检查代码115的主程序112执行错误检测/校正处理 并且将主程序112传送到第三存储装置13，之后CPU的控制分支到第三存储装置13上的主程序112.结果，可以执行系统引导而不使用NOR型闪存 。

公开(公告)号：US20050144430A1

公开(公告)日：2005-06-30

申请号：US11019054

申请日：2004-12-22

申请人： Yasunori Yamamoto ,  Keizo Sumida ,  Yoshiteru Mino

发明人： Yasunori Yamamoto ,  Keizo Sumida ,  Yoshiteru Mino

IPC分类号： G06F11/10 ,  G06F9/06 ,  G06F9/24 ,  G06F9/445 ,  G06F12/16

CPC分类号： G06F11/1417 ,  G06F11/1004

摘要： After power activation, a transferer 14 detects a bootstrap program 111 having a first error check code 114 assigned thereto and being stored in a first storage device 11, subjects the bootstrap program 111 to an error detection/correction process, and transfers the bootstrap program 111 to the second storage device 12. If the transfer is properly completed, by executing the bootstrap program 111 on the second storage device 12, the CPU 10 performs an error detection/correction process for a main program 112 having a second error check code 115 assigned thereto, and transfers the main program 112 to a third storage device 13, after which the CPU's control branches out to the main program 112 on the third storage device 13. As a result, system boot can be performed without employing a NOR type flash memory.

摘要翻译： 在电源激活之后，传送器14检测具有分配给其的第一错误检查码114并被存储在第一存储装置11中的自举程序111，使自举程序111进行错误检测/校正处理，并且传送引导程序111 到第二存储装置12。 如果传送正确完成，则通过在第二存储装置12上执行引导程序111，CPU10对分配有第二错误检查代码115的主程序112执行错误检测/校正处理，并且传送主程序 112到第三存储装置13，之后CPU的控制分支到第三存储装置13上的主程序112。 因此，可以在不使用NOR型闪存的情况下执行系统引导。

公开(公告)号：US20080082860A1

公开(公告)日：2008-04-03

申请号：US11984008

申请日：2007-11-13

申请人： Yasunori Yamamoto ,  Keizo Sumida ,  Yoshiteru Mino

发明人： Yasunori Yamamoto ,  Keizo Sumida ,  Yoshiteru Mino

IPC分类号： G06F11/16

CPC分类号： G06F11/1417 ,  G06F11/1004

摘要： After power activation, a transferer 14 detects a bootstrap program 111 having a first error check code 114 assigned thereto and being stored in a first storage device 11, subjects the bootstrap program 111 to an error detection/correction process, and transfers the bootstrap program 111 to the second storage device 12. If the transfer is properly completed, by executing the bootstrap program 111 on the second storage device 12, the CPU 10 performs an error detection/correction process for a main program 112 having a second error check code 115 assigned thereto, and transfers the main program 112 to a third storage device 13, after which the CPU's control branches out to the main program 112 on the third storage device 13. As a result, system boot can be performed without employing a NOR type flash memory.

摘要翻译： 在电源激活之后，传送器14检测具有分配给其的第一错误检查码114并被存储在第一存储装置11中的自举程序111，使自举程序111进行错误检测/校正处理，并且传送引导程序111 到第二存储装置12。 如果传送正确完成，则通过在第二存储装置12上执行引导程序111，CPU10对分配有第二错误检查代码115的主程序112执行错误检测/校正处理，并且传送主程序 112到第三存储装置13，之后CPU的控制分支到第三存储装置13上的主程序112。 因此，可以在不使用NOR型闪存的情况下执行系统引导。

公开(公告)号：US07308567B2

公开(公告)日：2007-12-11

申请号：US11019054

申请日：2004-12-22

申请人： Yasunori Yamamoto ,  Keizo Sumida ,  Yoshiteru Mino

发明人： Yasunori Yamamoto ,  Keizo Sumida ,  Yoshiteru Mino

IPC分类号： G06F9/445 ,  G06F15/177 ,  G06F9/24

CPC分类号： G06F11/1417 ,  G06F11/1004

摘要： After power activation, a transferer 14 detects a bootstrap program 111 having a first error check code 114 assigned thereto and being stored in a first storage device 11, subjects the bootstrap program 111 to an error detection/correction process, and transfers the bootstrap program 111 to the second storage device 12. If the transfer is properly completed, by executing the bootstrap program 111 on the second storage device 12, the CPU 10 performs an error detection/correction process for a main program 112 having a second error check code 115 assigned thereto, and transfers the main program 112 to a third storage device 13, after which the CPU's control branches out to the main program 112 on the third storage device 13. As a result, system boot can be performed without employing a NOR type flash memory.

摘要翻译： 在电源激活之后，传送器14检测具有分配给其的第一错误检查码114并被存储在第一存储装置11中的自举程序111，使自举程序111进行错误检测/校正处理，并且传送引导程序111 到第二存储装置12。 如果传送正确完成，则通过在第二存储装置12上执行引导程序111，CPU10对分配有第二错误检查代码115的主程序112执行错误检测/校正处理，并且传送主程序 112到第三存储装置13，之后CPU的控制分支到第三存储装置13上的主程序112。 因此，可以在不使用NOR型闪存的情况下执行系统引导。

公开(公告)号：US07516254B2

公开(公告)日：2009-04-07

申请号：US11470742

申请日：2006-09-07

申请人： Hidenori Nanki ,  Yoshiteru Mino ,  Keizo Sumida

发明人： Hidenori Nanki ,  Yoshiteru Mino ,  Keizo Sumida

IPC分类号： G06F5/00 ,  G06F13/28

CPC分类号： G06F13/1631

摘要： A memory control apparatus is capable of surely becoming consistent with an external memory while avoiding a deterioration in access efficiency to the external memory. The memory control apparatus includes: a data buffer and an address buffer which respectively store data and addresses related to past access requests from a first master; a first comparison unit which compares a new address with the address of the address buffer upon receiving the new address; a buffer control unit which performs one of issuing an access request to an external memory I/F or outputting the data in the data buffer to the first master, depending on the comparison result; a specific access detection unit which disables the contents of the data buffer irrespective of the comparison result.

摘要翻译： 存储器控制装置能够确保与外部存储器一致，同时避免对外部存储器的访问效率的劣化。 存储器控制装置包括：数据缓冲器和地址缓冲器，其分别存储与来自第一主机的过去访问请求相关的数据和地址; 第一比较单元，其在接收到新地址时将新地址与地址缓冲器的地址进行比较; 缓冲器控制单元，其根据比较结果执行向外部存储器I / F发出访问请求或将数据缓冲器中的数据输出到第一主机的一个; 特定访问检测单元，其与比较结果无关地禁用数据缓冲器的内容。

公开(公告)号：US20070294487A1

公开(公告)日：2007-12-20

申请号：US11808953

申请日：2007-06-14

申请人： Yoshiteru Mino ,  Keizo Sumida

发明人： Yoshiteru Mino ,  Keizo Sumida

IPC分类号： G06F13/00

CPC分类号： G06F13/161

摘要： The unified memory system includes: a memory accessed from a plurality of masters; a speculative access control section for issuing, in response to a first access request to the memory from a CPU as one of the plurality of masters, a speculative second access request to the memory; and a memory controller for receiving the first and second access requests and an access request to the memory from any of the plurality of masters other than the CPU and executing access to the memory. The speculative access control section issues the second access request according to speculative access information as information related to access to the memory.

摘要翻译： 统一存储器系统包括：从多个主器件访问的存储器; 推测访问控制部分，用于响应于从作为多个主人之一的CPU向存储器的第一访问请求向存储器发出推测性第二访问请求; 以及存储器控制器，用于从除CPU之外的多个主器件中的任一个接收第一和第二访问请求以及对存储器的访问请求，并执行对存储器的访问。 推测访问控制部分根据推测访问信息发布第二访问请求作为与访问存储器有关的信息。

公开(公告)号：US20070088855A1

公开(公告)日：2007-04-19

申请号：US11470742

申请日：2006-09-07

申请人： Hidenori NANKI ,  Yoshiteru Mino ,  Keizo Sumida

发明人： Hidenori NANKI ,  Yoshiteru Mino ,  Keizo Sumida

IPC分类号： G06F3/00

CPC分类号： G06F13/1631

摘要： A memory control apparatus is capable of surely becoming consistent with an external memory while avoiding a deterioration in access efficiency to the external memory. The memory control apparatus includes: a data buffer and an address buffer which respectively store data and addresses related to past access requests from a first master; a first comparison unit which compares a new address with the address of the address buffer upon receiving the new address; a buffer control unit which performs one of issuing an access request to an external memory I/F or outputting the data in the data buffer to the first master, depending on the comparison result; a specific access detection unit which disables the contents of the data buffer irrespective of the comparison result.

摘要翻译： 存储器控制装置能够确保与外部存储器一致，同时避免对外部存储器的访问效率的劣化。 存储器控制装置包括：数据缓冲器和地址缓冲器，其分别存储与来自第一主机的过去访问请求相关的数据和地址; 第一比较单元，其在接收到新地址时将新地址与地址缓冲器的地址进行比较; 缓冲器控制单元，其根据比较结果执行向外部存储器I / F发出访问请求或将数据缓冲器中的数据输出到第一主机的一个; 特定访问检测单元，其与比较结果无关地禁用数据缓冲器的内容。

公开(公告)号：USRE43145E1

公开(公告)日：2012-01-24

申请号：US11016920

申请日：2004-12-21

申请人： Toru Morikawa ,  Nobuo Higaki ,  Akira Miyoshi ,  Keizo Sumida

发明人： Toru Morikawa ,  Nobuo Higaki ,  Akira Miyoshi ,  Keizo Sumida

IPC分类号： G06F9/302

摘要： A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction “MCSST D1” is decoded, the sum-product result register 6 outputs its held value to the path P1. The comparator 22 compares the magnitude of the held value of the sum-product result register 6 with the coded 32-bit integer “0x0000_00FF”. The polarity judging unit 23 judges whether the eighth bit of the value held by the sum-product result register 6 is “ON”. The multiplexer 24 outputs one of the maximum value “0x0000_00FF” generated by the constant generator 21, the zero value “0x0000_0000” generated by the zero generator 25, and the held value of the sum-product result register 6 to the data bus 18.

摘要翻译： 执行正转换处理的处理器，其将编码数据转换为未编码数据，以及饱和度计算处理，其以高速将值舍入到适当位数。 当正转换饱和度计算指令“MCSST D1”被解码时，积和结果寄存器6将其保持值输出到路径P1。 比较器22将和积结果寄存器6的保持值的大小与编码的32位整数“0x0000_00FF”进行比较。 极性判断单元23判断由和积结果寄存器6保持的值的第8位是否为“ON”。 复用器24将由常数发生器21产生的最大值“0x0000_00FF”，由零发生器25产生的零值“0x0000_0000”和和积结果寄存器6的保持值输出到数据总线18中的一个。