公开(公告)号：USRE43729E1

公开(公告)日：2012-10-09

申请号：US13092453

申请日：2011-04-22

申请人： Toru Morikawa ,  Nobuo Higaki ,  Akira Miyoshi ,  Keizo Sumida

发明人： Toru Morikawa ,  Nobuo Higaki ,  Akira Miyoshi ,  Keizo Sumida

IPC分类号： G06F9/302

摘要： A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction “MCSST D1” is decoded, the sum-product result register 6 outputs its held value to the path P1. The comparator 22 compares the magnitude of the held value of the sum-product result register 6 with the coded 32-bit integer “0x0000_00FF”. The polarity judging unit 23 judges whether the eighth bit of the value held by the sum-product result register 6 is “ON”. The multiplexer 24 outputs one of the maximum value “0x0000_00FF” generated by the constant generator 21, the zero value “0x0000_0000” generated by the zero generator 25, and the held value of the sum-product result register 6 to the data bus 18.

摘要翻译： 执行正转换处理的处理器，其将编码数据转换为未编码数据，以及饱和度计算处理，其以高速将值舍入到适当位数。 当正转换饱和度计算指令MCSST D1被解码时，积和结果寄存器6将其保持值输出到路径P1。 比较器22将和积结果寄存器6的保持值的大小与编码的32位整数0x0000_00FF进行比较。 极性判定单元23判断由积分结果寄存器6保持的值的第八位是否为ON。 复用器24输出由常数发生器21产生的最大值0x0000_00FF，由零发生器25产生的零值0x0000_0000和和积结果寄存器6的保持值到数据总线18之一。

公开(公告)号：USRE39121E1

公开(公告)日：2006-06-06

申请号：US10366502

申请日：2003-02-13

申请人： Toru Morikawa ,  Nobuo Higaki ,  Akira Miyoshi ,  Keizo Sumida

发明人： Toru Morikawa ,  Nobuo Higaki ,  Akira Miyoshi ,  Keizo Sumida

IPC分类号： G06F9/302 ,  G06F7/38

CPC分类号： G06F9/3001 ,  G06F7/49921 ,  G06F7/5443 ,  G06F7/57

摘要： A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction “MCSST D1” is decoded, the sum-product result register 6 outputs its held value to the path P1. The comparator 22 compares the magnitude of the held value of the sum-product result register 6 with the coded 32-bit integer “0x0000_00FF”. The polarity judging unit 23 judges whether the eighth bit of the value held by the sum-product result register 6 is “ON”. The multiplexer 24 outputs one of the maximum value “0x0000_00FF” generated by the constant generator 21, the zero value “0x0000_0000” generated by the zero generator 25, and the held value of the sum-product result register 6 to the data bus 18.

摘要翻译： 执行正转换处理的处理器，其将编码数据转换为未编码数据，以及饱和度计算处理，其以高速将值舍入到适当位数。 当正转换饱和度计算指令“MCSST D 1”被解码时，积和结果寄存器6将其保持值输出到路径P 1。 比较器22将和积结果寄存器6的保持值的大小与编码的32位整数“0x0000_00FF”进行比较。 极性判断单元23判断由和积结果寄存器6保持的值的第8位是否为“ON”。 复用器24将由常数发生器21产生的最大值“0x0000_00FF”，由零发生器25产生的零值“0x0000_0000”和和积结果寄存器6的保持值输出到数据总线18中的一个。

公开(公告)号：US5974540A

公开(公告)日：1999-10-26

申请号：US980676

申请日：1997-12-01

申请人： Toru Morikawa ,  Nobuo Higaki ,  Akira Miyoshi ,  Keizo Sumida

发明人： Toru Morikawa ,  Nobuo Higaki ,  Akira Miyoshi ,  Keizo Sumida

IPC分类号： G06F7/544 ,  G06F7/57 ,  G06F9/302 ,  G06F7/38

CPC分类号： G06F9/3001 ,  G06F7/5443 ,  G06F7/57 ,  G06F7/49921

摘要： A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction "MCSST D1" is decoded, the sum-product result register 6 outputs its held value to the path P1. The comparator 22 compares the magnitude of the held value of the sum-product result register 6 with the coded 32-bit integer "0x0000.sub.-- 00FF". The polarity judging unit 23 judges whether the eighth bit of the value held by the sum-product result register 6 is "ON". The multiplexer 24 outputs one of the maximum value "0x0000.sub.-- 00FF" generated by the constant generator 21, the zero value "0x0000.sub.-- 0000" generated by the zero generator 25, and the held value of the sum-product result register 6 to the data bus 18.

摘要翻译： 执行正转换处理的处理器，其将编码数据转换为未编码数据，以及饱和度计算处理，其以高速将值舍入到适当位数。 当正转换饱和度计算指令“MCSST D1”被解码时，积和结果寄存器6将其保持值输出到路径P1。 比较器22将和积结果寄存器6的保持值的大小与编码的32位整数“0x0000-00FF”进行比较。 极性判断单元23判断由和积结果寄存器6保持的值的第8位是否为“ON”。 复用器24输出由常数发生器21产生的最大值“0x0000-00FF”，由零发生器25产生的零值“0x0000-0000”和和积结果寄存器6的保持值之一 数据总线18。

公开(公告)号：USRE43145E1

公开(公告)日：2012-01-24

申请号：US11016920

申请日：2004-12-21

申请人： Toru Morikawa ,  Nobuo Higaki ,  Akira Miyoshi ,  Keizo Sumida

发明人： Toru Morikawa ,  Nobuo Higaki ,  Akira Miyoshi ,  Keizo Sumida

IPC分类号： G06F9/302

摘要： A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction “MCSST D1” is decoded, the sum-product result register 6 outputs its held value to the path P1. The comparator 22 compares the magnitude of the held value of the sum-product result register 6 with the coded 32-bit integer “0x0000_00FF”. The polarity judging unit 23 judges whether the eighth bit of the value held by the sum-product result register 6 is “ON”. The multiplexer 24 outputs one of the maximum value “0x0000_00FF” generated by the constant generator 21, the zero value “0x0000_0000” generated by the zero generator 25, and the held value of the sum-product result register 6 to the data bus 18.

摘要翻译： 执行正转换处理的处理器，其将编码数据转换为未编码数据，以及饱和度计算处理，其以高速将值舍入到适当位数。 当正转换饱和度计算指令“MCSST D1”被解码时，积和结果寄存器6将其保持值输出到路径P1。 比较器22将和积结果寄存器6的保持值的大小与编码的32位整数“0x0000_00FF”进行比较。 极性判断单元23判断由和积结果寄存器6保持的值的第8位是否为“ON”。 复用器24将由常数发生器21产生的最大值“0x0000_00FF”，由零发生器25产生的零值“0x0000_0000”和和积结果寄存器6的保持值输出到数据总线18中的一个。

公开(公告)号：US06237084B1

公开(公告)日：2001-05-22

申请号：US09399577

申请日：1999-09-20

申请人： Toru Morikawa ,  Nobuo Higaki ,  Akira Miyoshi ,  Keizo Sumida

发明人： Toru Morikawa ,  Nobuo Higaki ,  Akira Miyoshi ,  Keizo Sumida

IPC分类号： G06F9302

CPC分类号： G06F9/3001 ,  G06F7/49921 ,  G06F7/5443 ,  G06F7/57

摘要： A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction “MCSST D1” is decoded, the sum-product result register 6 outputs its held value to the path P1. The comparator 22 compares the magnitude of the held value of the sum-product result register 6 with the coded 32-bit integer “0x0000_00FF”. The polarity judging unit 23 judges whether the eighth bit of the value held by the sum-product result register 6 is “ON”. The multiplexer 24 outputs one of the maximum value “0x0000_00FF” generated by the constant generator 21, the zero value “0x0000_0000” generated by the zero generator 25, and the held value of the sum-product result register 6 to the data bus 18.

摘要翻译： 执行正转换处理的处理器，其将编码数据转换为未编码数据，以及饱和度计算处理，其以高速将值舍入到适当位数。 当正转换饱和度计算指令“MCSST D1”被解码时，积和结果寄存器6将其保持值输出到路径P1。 比较器22将和积结果寄存器6的保持值的大小与编码的32位整数“0x0000_00FF”进行比较。 极性判断单元23判断由和积结果寄存器6保持的值的第8位是否为“ON”。 复用器24将由常数发生器21产生的最大值“0x0000_00FF”，由零发生器25产生的零值“0x0000_0000”和和积结果寄存器6的保持值输出到数据总线18中的一个。

公开(公告)号：US20130072617A1

公开(公告)日：2013-03-21

申请号：US13583581

申请日：2011-01-14

申请人： Yasuyuki Agari ,  Akira Miyoshi ,  Ryohei Tsuboi

发明人： Yasuyuki Agari ,  Akira Miyoshi ,  Ryohei Tsuboi

IPC分类号： C09D133/08 ,  C09D133/10 ,  C08K3/26

CPC分类号： C09D5/32 ,  C08K3/22 ,  C09D7/61 ,  C09D101/12 ,  C09D133/02

摘要： The present invention provides a transparent heat radiating coating composition capable of forming a coating layer having excellent transparency and heat radiating properties. The transparent heat radiating coating composition of the present invention is a transparent heat radiating coating composition including a binder resin, a hydrotalcite-series compound and a resin dispersant with an amine value of 0 to 90 mgKOH/g, wherein the transparent heat radiating coating composition includes 50 to 290 parts by weight of the hydrotalcite-series compound based on 100 parts by weight of the binder resin.

摘要翻译： 本发明提供一种能够形成透明性和散热性优异的涂层的透明散热涂料组合物。 本发明的透明散热用涂料组合物是包含粘合剂树脂，水滑石系列化合物和胺值为0​​至90mgKOH / g的树脂分散剂的透明散热涂料组合物，其中透明散热涂料组合物 基于100重量份的粘合剂树脂，包含50〜290重量份的水滑石系列化合物。

公开(公告)号：US07586461B2

公开(公告)日：2009-09-08

申请号：US11412547

申请日：2006-04-27

申请人： Akira Miyoshi ,  Takao Kato ,  Junichi Noro

发明人： Akira Miyoshi ,  Takao Kato ,  Junichi Noro

IPC分类号： H01Q1/36

CPC分类号： H01Q1/2216 ,  H01Q1/362 ,  H01Q11/08

摘要： An antenna unit comprises a hollow cylindrical member obtained by forming a flexible insulating film member into a hollow cylinder about a center axis and an antenna pattern composed of a plurality of conductors formed on a peripheral surface of the hollow cylindrical member. The antenna pattern comprises a helical pattern extending helically in a direction of the center axis and a loop pattern connected to an end portion of the helical pattern at an upper end portion of the hollow cylindrical member.

摘要翻译： 天线单元包括通过将柔性绝缘膜构件围绕中心轴形成为中空圆筒而获得的中空圆柱形构件和由形成在中空圆柱形构件的圆周表面上的多个导体构成的天线图案。 天线图案包括在中心轴线的方向上螺旋状延伸的螺旋图案和在中空圆柱形构件的上端部处连接到螺旋图案的端部的环形图案。

公开(公告)号：US20090058732A1

公开(公告)日：2009-03-05

申请号：US11988581

申请日：2006-03-02

申请人： Hisamatsu Nakano ,  Akira Miyoshi ,  Takaaki Kondo ,  Satoshi Hattori ,  Takaaki Kondo ,  Junji Yamauchi

发明人： Hisamatsu Nakano ,  Akira Miyoshi ,  Takaaki Kondo ,  Satoshi Hattori ,  Takaaki Kondo ,  Junji Yamauchi

IPC分类号： H01Q9/04

CPC分类号： H01Q9/40 ,  H01Q1/48 ,  H01Q9/30

摘要： To provide a thin wideband antenna unit capable of shrinking the size of a radiation element in a case where a dielectric is not used.In a wideband antenna unit 10 having a ground plate 12 and a flat shaped radiation element 14 disposed on a plane (x, y) flush with a plane where the ground plate extends, the radiation element 14 has an elliptically shape. The radiation element 14 and the ground plate 12 are apart from each other by a predetermined feeding distance ΔFD. A ratio between an outside diameter 2aout in an ellipse's x-direction and an outside diameter 2bout in an ellipse's y-direction is 8:5. The elliptically shaped radiation element 14 has an elliptically shaped opening 14a which is concentric O with the elliptically shape. An inside diameter 2bin in the ellipse's y-direction is half of an outside diameter 2bout in the ellipse's y-direction. It is desirable that an inside diameter 2ain of the elliptically shaped opening 14a in the ellipse's x-direction is not more than half of the outside diameter 2aout in the ellipse's x-direction.

摘要翻译： 为了提供在不使用电介质的情况下能够收缩辐射元件的尺寸的薄宽带天线单元。 在具有接地板12和设置在与接地板延伸的平面齐平的平面（x，y）上的平坦形状的辐射元件14的宽带天线单元10中，辐射元件14具有椭圆形。 辐射元件14和接地板12彼此隔开预定的馈送距离ΔFD。 椭圆x方向的外径2aout与椭圆y方向的外径2bo之间的比例为8:5。 椭圆形辐射元件14具有椭圆形的开口14a，其与椭圆形状同心O。 椭圆y方向的内径2bin是椭圆y方向的外径2bo的一半。 希望椭圆形x方向上的椭圆形开口14a的内径2ain不大于椭圆x方向上的外径2aout的一半。

公开(公告)号：US07463213B2

公开(公告)日：2008-12-09

申请号：US11699815

申请日：2007-01-30

申请人： Hisamatsu Nakano ,  Hidekazu Umetsu ,  Yoichi Asano ,  Junji Yamauchi ,  Akira Miyoshi

发明人： Hisamatsu Nakano ,  Hidekazu Umetsu ,  Yoichi Asano ,  Junji Yamauchi ,  Akira Miyoshi

IPC分类号： H01Q15/02 ,  H01Q1/38

CPC分类号： H01Q15/0053 ,  H01Q1/362 ,  H01Q11/08 ,  H01Q15/008 ,  H01Q15/142 ,  H01Q19/10

摘要： An antenna unit consists of an EBG reflector, a single curl antenna supported at a central portion of the EBG reflector, and a periodic structure upper plate disposed apart from a principal surface of the EBG reflector by a predetermined distance. The EBG reflector includes a substrate having the principal surface and (Nx×Ny) square patches which are printed on the principle surface of the substrate and which are arranged in a matrix fashion (lattice structure). The periodic structure upper plate consists of a film and (Nx×Ny) square patch-like conductors printed on the film. The (Nx×Ny) square patch-like conductors are disposed so as to oppose to the (Nx×Ny) square patches, respectively.

摘要翻译： 天线单元包括EBG反射器，支撑在EBG反射器的中心部分的单个卷曲天线以及与EBG反射器的主表面分开预定距离的周期性结构上板。 EBG反射器包括具有主表面的衬底和（NxxNy）个正方形贴片，印刷在衬底的主表面上并且以矩阵方式排列（晶格结构）。 周期性结构上板由薄膜和印在薄膜上的（NxxNy）方形贴片状导体组成。 （NxxNy）方形片状导体分别设置成与（NxxNy）个正方形块相对。

公开(公告)号：US07315934B2

公开(公告)日：2008-01-01

申请号：US10377328

申请日：2003-02-28

申请人： Hiroyuki Morishita ,  Atsushi Ito ,  Satoshi Takashima ,  Hideshi Nishida ,  Kozo Kimura ,  Tokuzo Kiyohara ,  Akira Miyoshi ,  Hiroshi Kadota

发明人： Hiroyuki Morishita ,  Atsushi Ito ,  Satoshi Takashima ,  Hideshi Nishida ,  Kozo Kimura ,  Tokuzo Kiyohara ,  Akira Miyoshi ,  Hiroshi Kadota

IPC分类号： G06F15/76

CPC分类号： G06F9/3012 ,  G06F9/30036 ,  G06F9/3824 ,  G06F9/3885

摘要： A data processor has sixteen processing elements that each include a register file and an arithmetic logic unit. A network unit connects between the register files of the processing elements and the arithmetic logic units of the processing elements. The network unit has a selector for simultaneously performing a plurality of data transfers which are each made from a register file of one processing element to an operation unit of another processing element. With the provision of this selector that can perform such simultaneous data transfers, the processing efficiency of the processing elements can be maintained even if a change occurs in operand assignments and the like.

摘要翻译： 数据处理器具有16个处理元件，每个处理元件包括寄存器文件和算术逻辑单元。 网络单元连接处理元件的寄存器文件和处理元件的算术逻辑单元。 网络单元具有选择器，用于同时执行多个数据传送，每个数据传输由一个处理元件的寄存器文件制成到另一个处理元件的操作单元。 通过提供可以执行这种同时数据传输的该选择器，即使在操作数分配等中发生改变，也可以保持处理元件的处理效率。