公开(公告)号：US10157123B1

公开(公告)日：2018-12-18

申请号：US15799013

申请日：2017-10-31

Applicant: Juniper Networks, Inc.

Inventor： Srinivas Vaduvatha ,  Deepak Goel ,  Shahriar Ilislamloo

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F3/06

Abstract: An apparatus includes a scheduler module operatively coupled to each memory block from a set of memory blocks via a shared address bus. The scheduler module is configured to receive a group of memory commands from a set of memory controllers. Each memory controller from the set of memory controllers is uniquely associated with a different memory block from the set of memory blocks. The scheduler module is configured to classify each memory command from the group of memory commands into a category based at least in part on memory commands previously sent to the set of memory blocks via the shared address bus. The scheduler module is configured to select an order in which to send each memory command from the group of memory commands to the set of memory blocks via the shared address bus based at least in part on the category of each memory command.

公开(公告)号：US09811453B1

公开(公告)日：2017-11-07

申请号：US13955733

申请日：2013-07-31

Applicant: Juniper Networks, Inc.

Inventor： Srinivas Vaduvatha ,  Deepak Goel ,  Shahriar Ilislamloo

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F3/06

CPC classification number: G06F12/00 ,  G06F3/0659 ,  G06F13/16 ,  G06F13/1631 ,  G06F2212/1016 ,  G06F2212/1024

Abstract: An apparatus includes a scheduler module operatively coupled to each memory block from a set of memory blocks via a shared address bus. The scheduler module is configured to receive a group of memory commands from a set of memory controllers. Each memory controller from the set of memory controllers is uniquely associated with a different memory block from the set of memory blocks. The scheduler module is configured to classify each memory command from the group of memory commands into a category based at least in part on memory commands previously sent to the set of memory blocks via the shared address bus. The scheduler module is configured to select an order in which to send each memory command from the group of memory commands to the set of memory blocks via the shared address bus based at least in part on the category of each memory command.