公开(公告)号：US08813015B2

公开(公告)日：2014-08-19

申请号：US13725215

申请日：2012-12-21

Applicant: Juniper Networks, Inc.

Inventor： Srinivas Vaduvatha ,  Srinivas Venkataraman ,  Anurag P. Gupta ,  Praveen Garapally ,  Norman Bristol ,  Dibyendu Sen

IPC: G06F17/50 ,  G06F12/00 ,  G06F13/40

CPC classification number: G06F12/00 ,  G06F13/409

Abstract: A system includes a memory and a controller. The controller may include a group of pads and an allocation register. The controller is configured to receive input signals corresponding to the group and allocate each one of the pads to output one of the input signals based on a configuration of pins of the memory. The controller is also configured to redirect the input signals, within the controller, based on the allocation of the pads and output the input signals from the controller into the pads.

Abstract translation: 系统包括存储器和控制器。 控制器可以包括一组焊盘和分配寄存器。 控制器被配置为接收对应于组的输入信号，并且基于存储器的引脚的配置来分配每个焊盘以输出输入信号之一。 控制器还被配置为基于焊盘的分配来重定向控制器内的输入信号，并将输入信号从控制器输出到焊盘中。

公开(公告)号：US10157123B1

公开(公告)日：2018-12-18

申请号：US15799013

申请日：2017-10-31

Applicant: Juniper Networks, Inc.

Inventor： Srinivas Vaduvatha ,  Deepak Goel ,  Shahriar Ilislamloo

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F3/06

Abstract: An apparatus includes a scheduler module operatively coupled to each memory block from a set of memory blocks via a shared address bus. The scheduler module is configured to receive a group of memory commands from a set of memory controllers. Each memory controller from the set of memory controllers is uniquely associated with a different memory block from the set of memory blocks. The scheduler module is configured to classify each memory command from the group of memory commands into a category based at least in part on memory commands previously sent to the set of memory blocks via the shared address bus. The scheduler module is configured to select an order in which to send each memory command from the group of memory commands to the set of memory blocks via the shared address bus based at least in part on the category of each memory command.

公开(公告)号：US09811453B1

公开(公告)日：2017-11-07

申请号：US13955733

申请日：2013-07-31

Applicant: Juniper Networks, Inc.

Inventor： Srinivas Vaduvatha ,  Deepak Goel ,  Shahriar Ilislamloo

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F3/06

CPC classification number: G06F12/00 ,  G06F3/0659 ,  G06F13/16 ,  G06F13/1631 ,  G06F2212/1016 ,  G06F2212/1024

Abstract: An apparatus includes a scheduler module operatively coupled to each memory block from a set of memory blocks via a shared address bus. The scheduler module is configured to receive a group of memory commands from a set of memory controllers. Each memory controller from the set of memory controllers is uniquely associated with a different memory block from the set of memory blocks. The scheduler module is configured to classify each memory command from the group of memory commands into a category based at least in part on memory commands previously sent to the set of memory blocks via the shared address bus. The scheduler module is configured to select an order in which to send each memory command from the group of memory commands to the set of memory blocks via the shared address bus based at least in part on the category of each memory command.