公开(公告)号：US20020075205A1

公开(公告)日：2002-06-20

申请号：US09996742

申请日：2001-11-30

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Hiroyuki Kimura ,  Takashi Maeda ,  Takanori Tsunashima

IPC: G09G003/20

CPC classification number: G09G3/3659 ,  G09G3/2011 ,  G09G3/3614 ,  G09G2300/0814 ,  G09G2300/0823 ,  G09G2300/0833 ,  G09G2300/0842 ,  G09G2320/10 ,  G09G2330/021 ,  G09G2340/0428

Abstract: Disclosed is a circuit constitution of a display apparatus comprising a digital memory (DM) cell for each pixel. The DM cell is composed of one inverter circuit, and a DM switching circuit for controlling an electrical conduction between a pixel electrode and the DM cell is provided. During a normal displaying period, the DM cell and the pixel electrode are not electrically conducted by the DM switching circuit, and a full-color image displaying is performed by dynamic image data supplied to a signal line. During a still image displaying, the DM cell and the pixel electrode are electrically conducted by the DM switching circuit, and a multi-color image displaying is performed by still image data retained in the DM cell.

Abstract translation: 公开了包括用于每个像素的数字存储器（DM）单元的显示装置的电路结构。 DM单元由一个反相器电路组成，并且提供用于控制像素电极和DM单元之间的导电的DM切换电路。 在正常显示期间，DM单元和像素电极不由DM切换电路进行导电，并且通过提供给信号线的动态图像数据进行全色图像显示。 在静止图像显示期间，DM单元和像素电极由DM切换电路导电，并且通过保留在DM单元中的静止图像数据执行多色图像显示。

公开(公告)号：US20030174116A1

公开(公告)日：2003-09-18

申请号：US10325937

申请日：2002-12-23

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Takashi Maeda ,  Takanori Tsunashima ,  Hiroyuki Kimura

IPC: G09G003/36

CPC classification number: G09G3/3659 ,  G09G2300/0809 ,  G09G2300/0857

Abstract: During a still picture display period, a normal write voltage is sometimes unable to be applied to a liquid crystal layer 16 because two memory switch elements 21 and 22 are simultaneously turned on, and the output and the inverted output from the digital memory 18 are applied simultaneously to a pixel electrode 13. According to the present invention, the pulse width for the on period of one of the memory switch elements 21 and 22 is narrower than the pulse width for the off period of the other memory switch element, so that the on periods of the two memory switch elements 21 and 22 do not overlap. In this manner, the memory switch elements 21 and 22 are prevented from being turned on at the same time.

Abstract translation: 在静止图像显示期间，由于两个存储器开关元件21和22同时导通，所以正常的写入电压有时不能施加到液晶层16，并且应用来自数字存储器18的输出和反相输出 根据本发明，一个存储开关元件21和22的导通周期的脉冲宽度比另一个存储器开关元件的截止周期的脉冲宽度窄，因此， 两个存储开关元件21和22的周期不重叠。 以这种方式，防止存储器开关元件21和22同时导通。

公开(公告)号：US20010024187A1

公开(公告)日：2001-09-27

申请号：US09812571

申请日：2001-03-21

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Hajime Sato ,  Hiroyuki Kimura ,  Takashi Maeda ,  Takanori Tsunashima

IPC: G09G003/36

CPC classification number: G09G3/3659 ,  G02F1/136 ,  G09G2300/0857 ,  G09G2320/10 ,  G09G2330/021

Abstract: A display has display pixels provided with digital memories, respectively. In each display pixel, a pixel electrode and a data line are connected to each other through a first switch, and the pixel electrode and the digital memory are connected to each other through a second switch. In a first display period, the second switches are turned off and the first switches are turned on, to display video data supplied from the data lines. In a second display period, the second switches are turned on and the first switches are turned off, to stop scan and data drivers and display video data stored in the digital memories.

Abstract translation: 显示器分别具有设置有数字存储器的显示像素。 在每个显示像素中，像素电极和数据线通过第一开关彼此连接，并且像素电极和数字存储器通过第二开关相互连接。 在第一显示周期中，第二开关断开，第一开关导通，以显示从数据线提供的视频数据。 在第二显示期间，第二开关导通，第一开关断开，停止扫描和数据驱动并显示数字存储器中存储的视频数据。