公开(公告)号：US11777475B2

公开(公告)日：2023-10-03

申请号：US17829126

申请日：2022-05-31

申请人： KANDOU LABS, S.A.

发明人： Armin Tajalli ,  Yohann Mogentale ,  Fabio Licciardello

IPC分类号： H03K3/03 ,  H03B5/24 ,  H03K5/00 ,  H03L7/099

CPC分类号： H03K3/0322 ,  H03B5/24 ,  H03K2005/00208 ,  H03L7/0995

摘要： Methods and systems are described for generating multiple phases of a local clock at a controllable variable frequency, using loop-connected strings of active circuit elements. A specific embodiment incorporates a loop of four active circuit elements, each element providing true and complement outputs that are cross-coupled to maintain a fixed phase relationship, and feed-forward connections at each loop node to facilitate high frequency operation. A particular physical layout is described that maximizes operating frequency and minimizes clock pertubations caused by unbalanced or asymmetric signal paths and parasitic node capacitances.

公开(公告)号：US20220294432A1

公开(公告)日：2022-09-15

申请号：US17829126

申请日：2022-05-31

申请人： KANDOU LABS, S.A.

发明人： Armin Tajalli ,  Yohann Mogentale ,  Fabio Licciardello

IPC分类号： H03K3/03 ,  H03B5/24

摘要： Methods and systems are described for generating multiple phases of a local clock at a controllable variable frequency, using loop-connected strings of active circuit elements. A specific embodiment incorporates a loop of four active circuit elements, each element providing true and complement outputs that are cross-coupled to maintain a fixed phase relationship, and feed-forward connections at each loop node to facilitate high frequency operation. A particular physical layout is described that maximizes operating frequency and minimizes clock pertubations caused by unbalanced or asymmetric signal paths and parasitic node capacitances.