公开(公告)号：US20190165798A1

公开(公告)日：2019-05-30

申请号：US16264992

申请日：2019-02-01

申请人： DENSO CORPORATION

发明人： Kazuhiro NAGAI ,  Takuya HARADA

IPC分类号： H03L7/099 ,  H03K3/03

CPC分类号： H03K3/0315 ,  H03K3/013 ,  H03K5/156 ,  H03L7/0995

摘要： A ring oscillator is configured with a multiple number of logic inverting circuits in a ring shape and generates multi-phase clock signals. A period measuring unit measures a period of a reference clock inputted thereto by the multi-phase clock signals of the ring oscillator and outputs a measured period as a period data value. A frequency spreading calculation unit calculates a frequency spreading command value in accordance with a frequency spreading rate, a frequency spreading period and the period data value of the period measuring unit, which are inputted. A pulse generation unit generates a clock pulse corresponding to the frequency spreading command value in accordance with a data value determined by addition of the frequency spreading command value to the period data value.

公开(公告)号：US20190089358A1

公开(公告)日：2019-03-21

申请号：US15711708

申请日：2017-09-21

申请人： Qualcomm Incorporated

发明人： Ayush Mittal ,  Gajanan Maroti Devpuje ,  Bhushan Shanti Asuri ,  Krishnaswamy Thiagarajan

IPC分类号： H03L7/07 ,  H03L7/081 ,  H03L7/089 ,  H03L7/099 ,  H03K5/133

CPC分类号： H03L7/07 ,  H03K5/133 ,  H03L7/0812 ,  H03L7/0814 ,  H03L7/0891 ,  H03L7/093 ,  H03L7/0995

摘要： An integrated circuit is disclosed that implements a delay-locked loop with differential delay lines. In an example aspect, the integrated circuit includes a first delay line, a second delay line, and control circuitry. The first and second delay lines are coupled to a reference clock source to receive a reference clock. The first delay line produces a first delayed signal that is delayed relative to the reference clock by a first delay amount. The second delay line produces a second delayed signal that is delayed relative to the reference clock by a second delay amount. The control circuitry is coupled to the first and second delay lines. The control circuitry is configured to receive the first delayed signal, to receive the second delayed signal, and to adjust the first delay amount or the second delay amount based on the first delayed signal and the second delayed signal.

公开(公告)号：US20180254882A1

公开(公告)日：2018-09-06

申请号：US15707889

申请日：2017-09-18

申请人： John W. Bogdan

发明人： John W. Bogdan

IPC分类号： H04L7/00 ,  H04L27/26 ,  H03L7/099 ,  H03L7/085

CPC分类号： H04L7/0087 ,  H03L7/085 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/22 ,  H04L27/2655 ,  H04L27/2656 ,  H04L27/2685 ,  H04L27/2688

摘要： The Synthesizing Clock of OFDM Receiver (SCOR) is comprising methods and systems for synthesizing the OFDM receiver clock from a local clock in a feed-forward configuration, wherein the local clock is aligned in frequency to a received OFDM signal by using a frequency locked loop (FLL).

公开(公告)号：US09998128B2

公开(公告)日：2018-06-12

申请号：US14681455

申请日：2015-04-08

申请人： Infineon Technologies AG

发明人： Werner Grollitsch

IPC分类号： H03K3/03 ,  H03L7/099 ,  H03L7/087 ,  H03L7/24 ,  H03L7/091 ,  H03L7/197 ,  H03L7/18 ,  H03L7/08

CPC分类号： H03L7/0995 ,  H03K3/0315 ,  H03K3/0322 ,  H03L1/00 ,  H03L7/0802 ,  H03L7/087 ,  H03L7/091 ,  H03L7/099 ,  H03L7/0997 ,  H03L7/18 ,  H03L7/1974 ,  H03L7/22 ,  H03L7/24

摘要： Representative implementations of devices and techniques provide reduced jitter for a controlled oscillator. An edge of a reference signal is injected at various points within the oscillator, and is replaced for an edge of the generated oscillation signal at the injection point.

公开(公告)号：US20180102782A1

公开(公告)日：2018-04-12

申请号：US15288339

申请日：2016-10-07

申请人： ANALOG DEVICES, INC.

发明人： Hyman Shanan

IPC分类号： H03L7/099 ,  H03B5/04

CPC分类号： H03L7/0995 ,  G04F10/005 ,  H03B5/1841 ,  H03B5/1852 ,  H03B2200/0016 ,  H03L2207/50

摘要： Apparatus and methods for rotary traveling wave oscillators (RTWOs) are provided herein. In certain configurations, an RTWO includes a differential transmission line connected in a ring and a plurality of segments distributed around the ring. The segments include metal stubs extending from the RTWO's differential transmission line. The metal stubs aid in providing access to additional layout resources for tuning capacitors and other circuitry of the RTWO's segments, while permitting the length of RTWO's ring to be relative short. Thus, the metal stubs do not inhibit the RTWO from operating with relatively high oscillation frequency, while providing connectivity to tuning capacitors that tune the RTWO's oscillation frequency over a wide tuning range and/or provide fine frequency step size.

公开(公告)号：US20180069740A1

公开(公告)日：2018-03-08

申请号：US15688858

申请日：2017-08-28

申请人： John W Bogdan

发明人： John W Bogdan

IPC分类号： H04L27/26 ,  H04L25/03 ,  H04L7/00 ,  H03H17/02 ,  H03H17/04

CPC分类号： H04L27/2656 ,  H03H17/0251 ,  H03H17/04 ,  H03L7/00 ,  H03L7/091 ,  H03L7/0995 ,  H03L7/16 ,  H03L7/22 ,  H04L7/0037 ,  H04L7/0087 ,  H04L25/0398 ,  H04L27/2657 ,  H04L27/2695

摘要： The data recovery from sub-carriers (DRSC) of a received OFDM signal, contributes a method and a circuit for utilizing parameters of OFDM sub-carriers comprised in the received OFDM signal or subspaces comprising the OFDM sub-carriers for recovering transmitted data symbols from the received OFDM signal affected by deterministic and random distortions introduced by a transmission link.

公开(公告)号：US20180069556A1

公开(公告)日：2018-03-08

申请号：US15644632

申请日：2017-07-07

申请人： Rambus Inc.

发明人： Jared L. Zerbe ,  Brian S. Leibowitz ,  Masum Hossain

IPC分类号： H03L7/16 ,  H03L7/24 ,  H03L7/099 ,  H03K5/00 ,  H03L7/06 ,  H03K3/03 ,  H03K5/14 ,  H03K5/13

CPC分类号： H03L7/16 ,  H03J2200/10 ,  H03K3/0315 ,  H03K5/00006 ,  H03K5/13 ,  H03K5/14 ,  H03L7/06 ,  H03L7/0995 ,  H03L7/24

摘要： In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.

公开(公告)号：US20180048321A1

公开(公告)日：2018-02-15

申请号：US15789035

申请日：2017-10-20

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Jingdong DENG ,  Chung S. HO ,  David FLYE ,  Zhenrong JIN ,  Ramana M. MALLADI

IPC分类号： H03L7/087 ,  H03L7/099 ,  G06F17/50

CPC分类号： H03L7/087 ,  G06F17/5045 ,  H03L7/0991 ,  H03L7/0995 ,  H03L7/0997 ,  H03L2207/06 ,  H03L2207/50 ,  H05K999/99

摘要： A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.

公开(公告)号：US20180026646A1

公开(公告)日：2018-01-25

申请号：US15218638

申请日：2016-07-25

申请人： SanDisk Technologies LLC

发明人： Bhavin Odedara ,  Srikanth Bojja ,  Jayanth Mysore Thimmaiah ,  Srinivasa Rao Sabbineni

IPC分类号： H03L7/099 ,  H03L7/093 ,  H03B27/00 ,  H03L7/089

CPC分类号： H03L7/099 ,  H03B27/00 ,  H03L7/0891 ,  H03L7/093 ,  H03L7/0995 ,  H03L7/0997 ,  H03L2207/06

摘要： A phase-locked loop (PLL) circuit may be configured to generate a plurality of oscillating signals based on a single control voltage generated based on a phase difference between an input signal and a feedback signal. One of the plurality of oscillating signals may be used to generate the feedback signal.

公开(公告)号：US20180019757A1

公开(公告)日：2018-01-18

申请号：US15545893

申请日：2015-05-22

申请人： Circuit Seed, LLC

发明人： Susan Marya Schober ,  Robert C. Schober ,  Herbert Shapiro

IPC分类号： H03L7/099 ,  H03K3/354 ,  H03B5/12 ,  H03L7/04 ,  H03K3/03

CPC分类号： H03L7/0995 ,  H03B5/12 ,  H03K3/0315 ,  H03K3/0322 ,  H03K3/354 ,  H03L7/04 ,  H03L7/0891 ,  H03L7/091 ,  H03L7/24 ,  H03L2207/06 ,  H03L2207/10

摘要： The present invention relates to passive phased injection locked circuit and ring-based voltage controlled oscillators. passive phased injection locked circuit comprises first and second transmission lines, each has a plurality of discrete elements, that are operative to deley the phase of AC signal. Between the first and second transmission lines, a capacitor network is formed to advance the phases of the AC signal in concert along the transmission lines. For the ring-based voltage controlled oscillators, each of the first and second transmission lines has an odd number of discrete elements.