公开(公告)号：US20230075492A1

公开(公告)日：2023-03-09

申请号：US17680121

申请日：2022-02-24

Applicant: KIOXIA CORPORATION

Inventor： Akiyuki KANEKO

IPC: G06F3/06

Abstract: A memory system includes a plurality of non-volatile memory chips and a controller configured to communicate with a host and control the plurality of non-volatile memory chips. The controller is configured to write a data frame that includes write data and a first parity for error detection and correction of the write data into first memory chips of the non-volatile memory chips in a distributed manner. The first memory chips includes N (N is a natural number of two or more) memory chips. The controller is configured to write a second parity for restoring data stored in one of the N first memory chips using data read from the other N−1 of the N first memory chips, into a second memory chip of the non-volatile memory chips that is different from any of the first memory chips.

公开(公告)号：US20220283741A1

公开(公告)日：2022-09-08

申请号：US17459956

申请日：2021-08-27

Applicant: KIOXIA CORPORATION

Inventor： Akiyuki KANEKO

IPC: G06F3/06 ,  G06F12/02

Abstract: A memory system includes a nonvolatile memory and a controller. The nonvolatile memory has first regions in which data writes and data reads can be executed in parallel. Each of the first regions has second regions which are each a data write/read unit. The controller acquires first values indicating a data write load for each of the first regions, detects a first region having a first value greater than or equal to a first threshold, acquires second values indicating a data write load for each of the plurality of second regions in the detected first region, detects a second region having a second value greater than or equal to a second threshold but less than or equal to a third threshold that is higher than the second threshold, and then move data from the detected second region to a second region in another first region.

公开(公告)号：US20210279005A1

公开(公告)日：2021-09-09

申请号：US17184218

申请日：2021-02-24

Applicant: KIOXIA CORPORATION

Inventor： Zheye WANG ,  Akiyuki KANEKO

IPC: G06F3/06

Abstract: According to one embodiment, a memory circuit includes a plurality of nonvolatile memory cells and a control circuit. Each of the plurality of nonvolatile memory cells loses stored data when the stored data is read. The control circuit reads data from a first memory cell among the plurality of memory cells as designated by a first instruction but does not write the data read from the first memory cell back to the first memory cell after the first instruction is received. The control circuit reads data from a second memory cell among the plurality of memory cells as designated by a second instruction and writes the data read from the second memory cell back to the second memory cell after the second instruction is received.

公开(公告)号：US20240176537A1

公开(公告)日：2024-05-30

申请号：US18459979

申请日：2023-09-01

Applicant: Kioxia Corporation

Inventor： Akiyuki KANEKO

IPC: G06F3/06

CPC classification number: G06F3/0658 ,  G06F3/0656 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory controller of a memory system includes a host interface, a memory interface, and a write buffer configured to temporarily store data of a second size that is greater than a first size of a sector in each of a plurality of entries. Each of the entries includes a plurality of sectors. The memory controller is configured to select one of the entries in which write data is to be stored, determine whether the selected entry is missing data of any sector, perform a host inquiry by transmitting a request for the missing data, store the missing data in the selected entry, and then perform a write operation to store the data of the selected entry into the nonvolatile memory at a continuous physical address range of the nonvolatile memory.

公开(公告)号：US20230062773A1

公开(公告)日：2023-03-02

申请号：US17686285

申请日：2022-03-03

Applicant: KIOXIA CORPORATION

Inventor： Akiyuki KANEKO

IPC: G06F3/06

Abstract: A nonvolatile memory includes a memory element, a buffer, and a control circuit that controls writing of data into the memory element or reading of data from the memory element. The control circuit reads data requested in a first command from the memory element when the first command is received, and stores the data in the buffer. In response to a second command that includes write data, the control circuit compares the write data with the data stored in the buffer, and writes only a portion of the write data that is different from the data stored in the buffer in to the memory element.