公开(公告)号：US20220285546A1

公开(公告)日：2022-09-08

申请号：US17553109

申请日：2021-12-16

Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Shinhyun Choi ,  Beomjin Kim ,  Tae Ryong Kim ,  See On Park

IPC: H01L29/788 ,  H01L29/49 ,  G11C16/24

Abstract: Provided is a floating gate based 3-terminal analog synapse device including a silicon channel layer; a gate oxide deposited on the silicon channel layer; a charge trap layer deposited on the gate oxide, wherein charges are injected into the charge trap layer; a barrier layer deposited on the charge trap layer, and having lower electron affinity than electron affinity of a material of the charge trap layer; and a gate metal layer deposited on an upper surface of the barrier layer, wherein a gate voltage is applied to the gate metal layer.

公开(公告)号：US12237426B2

公开(公告)日：2025-02-25

申请号：US17553109

申请日：2021-12-16

Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Shinhyun Choi ,  Beomjin Kim ,  Tae Ryong Kim ,  See On Park

IPC: H01L29/788 ,  G06F17/16 ,  G11C16/14 ,  G11C16/24 ,  G11C16/26 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/792

Abstract: Provided is a floating gate based 3-terminal analog synapse device including a silicon channel layer; a gate oxide deposited on the silicon channel layer; a charge trap layer deposited on the gate oxide, wherein charges are injected into the charge trap layer; a barrier layer deposited on the charge trap layer, and having lower electron affinity than electron affinity of a material of the charge trap layer; and a gate metal layer deposited on an upper surface of the barrier layer, wherein a gate voltage is applied to the gate metal layer.