公开(公告)号：US20160343810A1

公开(公告)日：2016-11-24

申请号：US14854221

申请日：2015-09-15

Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Sanghyeon KIM ,  Daemyeong GEUM ,  Min Su PARK ,  Won Jun CHOI

IPC: H01L29/205 ,  H01L21/78 ,  H01L29/165 ,  H01L21/683 ,  H01L21/18

CPC classification number: H01L21/78 ,  H01L21/185 ,  H01L21/6835 ,  H01L29/267 ,  H01L29/66219 ,  H01L29/861 ,  H01L31/0304 ,  H01L31/184 ,  H01L31/1892 ,  Y02E10/544

Abstract: Disclosed is a method for manufacturing a semiconductor device, which includes providing a template having a first substrate and a patterned first III-V group compound layer located on the first substrate, forming a sacrificial layer on the patterned first III-V group compound layer by epitaxial growth, forming a second III-V group compound layer on the sacrificial layer by epitaxial growth, bonding a second substrate made of silicon onto the second III-V group compound layer, and separating the second III-V group compound layer and the second substrate from the template by removing the sacrificial layer.

Abstract translation: 公开了一种制造半导体器件的方法，其包括提供具有第一衬底和位于第一衬底上的图案化的第一III-V族化合物层的模板，在图案化的第一III-V族化合物层上形成牺牲层， 外延生长，通过外延生长在牺牲层上形成第二III-V族化合物层，将由硅制成的第二衬底接合到第二III-V族化合物层上，以及将第二III-V族化合物层和第二III-V族化合物层分离 通过去除牺牲层从模板的衬底。