公开(公告)号：US20190316968A1

公开(公告)日：2019-10-17

申请号：US16451736

申请日：2019-06-25

Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY ,  UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Seung Hyub BAEK ,  Tae Hyeon KIL ,  Sanghyeon KIM ,  Won Jun CHOI ,  Jeong Min BAIK ,  Ki-Suk LEE

IPC: G01J5/22 ,  H01L49/02 ,  H01C17/12 ,  H01C7/00

Abstract: Disclosed is a resistor thin film for micro-bolometer for growth of a vanadium dioxide (VO2) thin film in monoclinic VO2 crystal phase by deposition of VO2 on oxide with perovskite structure and a method for fabricating the same, and the resistor thin film for micro-bolometer according to the present disclosure includes a silicon substrate, an oxide thin film with perovskite structure formed on the silicon substrate, and a VO2 thin film in monoclinic crystal phase formed on the oxide thin film with perovskite structure.

公开(公告)号：US20180335341A1

公开(公告)日：2018-11-22

申请号：US15926366

申请日：2018-03-20

Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY ,  UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Seung Hyub BAEK ,  Tae Hyeon KIL ,  Sanghyeon KIM ,  Won Jun CHOI ,  Jeong Min BAIK ,  Ki-Suk LEE

IPC: G01J1/42 ,  G01J5/20

CPC classification number: G01J1/42 ,  G01J5/024 ,  G01J5/046 ,  G01J5/20

Abstract: Disclosed is a resistor thin film for micro-bolometer for growth of a vanadium dioxide (VO2) thin film in tetragonal VO2 crystal phase by deposition of VO2 on oxide with perovskite structure and a method for fabricating the same, and the resistor thin film for micro-bolometer according to the present disclosure includes a silicon substrate, an oxide thin film with perovskite structure formed on the silicon substrate, and a VO2 thin film in tetragonal crystal phase formed on the oxide thin film with perovskite structure.

公开(公告)号：US20180076084A1

公开(公告)日：2018-03-15

申请号：US15416727

申请日：2017-01-26

Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Hyung-Jun KIM ,  Sanghyeon KIM ,  Jae-Phil SHIM ,  Yeon-Su KIM ,  Heejeong LIM

IPC: H01L21/762 ,  H01L21/02 ,  H01L29/06 ,  H01L29/16

Abstract: A method for manufacturing a semiconductor device includes: forming a sacrificial layer on a first substrate, the sacrificial layer being made of a material whose lattice constant is different from that of germanium (Ge) by a preset threshold or below; forming a germanium (Ge) layer on the sacrificial layer; forming an insulation layer on a second substrate; bonding the germanium (Ge) layer onto the insulation layer; and removing the sacrificial layer and the first substrate by etching the sacrificial layer in a state where the germanium (Ge) layer is bonded to the insulation layer. In this method, a germanium-on-insulator (GeOI) structure having various surface orientations may be formed by means of epitaxial lift-off (ELO), and a strain may be applied to the germanium (Ge) layer using a lattice constant of the sacrificial layer.

公开(公告)号：US20200041825A1

公开(公告)日：2020-02-06

申请号：US16528633

申请日：2019-08-01

Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Jae-Hoon HAN ,  Sanghyeon KIM ,  Pavlo BIDENKO ,  Subin LEE ,  Jin-Dong SONG

IPC: G02F1/05

Abstract: An optical phase shifter according to an embodiment for achieving the object of the present disclosure includes a first semiconductor layer formed on a substrate, a second semiconductor layer having opposite polarity to the first semiconductor layer, an insulating layer formed between the first semiconductor layer and the second semiconductor layer, and including ferroelectrics, a first electrode connected to the first semiconductor layer, and a second electrode connected to the second semiconductor layer. According to an embodiment, the introduction of ferroelectric materials to a semiconductor-insulator-semiconductor (SIS) optical phase shifter brings about improvement in charge collection efficiency resulting from the negative capacitance effect, thereby achieving higher phase modulation efficiency and lower power consumption. Additionally, it is possible to realize a new structure of optical switch or modulator device through design changes of the type of ferroelectrics and the structural variables.

公开(公告)号：US20180350988A1

公开(公告)日：2018-12-06

申请号：US15955690

申请日：2018-04-18

Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Hyung-jun KIM ,  Sanghyeon KIM ,  Jae-Phil SHIM

IPC: H01L29/78 ,  H01L29/20 ,  H01L29/16 ,  H01L29/66

Abstract: Disclosed is a semiconductor device, which includes: forming a first channel layer including a Group III-V compound or germanium (Ge) and having a first semiconductor characteristics on a first substrate; forming a second channel layer including a Group III-V compound or germanium (Ge) and having a second semiconductor characteristics different from the first semiconductor characteristics on the first channel layer; forming a bonding layer containing an oxide on a second channel layer; allowing the bonding layer to be bound to the second substrate so that a structure including the bonding layer, the second channel layer, the first channel layer and the first substrate may be stacked on the second substrate; removing the first substrate stacked on the second substrate; and removing the first channel layer from a partial region of the structure stacked on the second substrate.

公开(公告)号：US20180082900A1

公开(公告)日：2018-03-22

申请号：US15631309

申请日：2017-06-23

Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Sanghyeon KIM ,  Hyung-jun KIM ,  Jae-Phil SHIM ,  Seong Kwang KIM ,  Won Jun CHOI

IPC: H01L21/78 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L21/7813 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02392 ,  H01L21/02395 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/02516 ,  H01L21/30617

Abstract: A method for manufacturing a semiconductor device by epitaxial lift-off includes: forming a sacrificial layer containing an III-V compound on a first substrate, forming a device layer on the sacrificial layer, patterning the sacrificial layer and the device layer into a shape having an extending portion along a first direction determined based on a surface orientation of the III-V compound of the sacrificial layer, bonding the patterned device layer onto a second substrate, and etching the sacrificial layer by using an etching solution in a state where the device layer is bonded onto the second substrate, to remove the sacrificial layer and the first substrate. Using the method for manufacturing a semiconductor device, it is possible to improve a process yield and increase a process speed by using the difference in etch rates depending on crystal orientation, which is an inherent characteristic of an III-V compound, during an ELO process.

公开(公告)号：US20190312654A1

公开(公告)日：2019-10-10

申请号：US16376672

申请日：2019-04-05

Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Jaehoon HAN ,  Sanghyeon KIM ,  Hyunsu JU ,  Jin-Dong SONG

IPC: H04B10/80 ,  H04B10/66 ,  H04B10/50

Abstract: A method for optical interconnection between semiconductor chips according to an embodiment include converting an electrical signal to an optical signal, transmitting the optical signal to a second substrate disposed above or below a first substrate using an optical transmitter provided on the first substrate, receiving the optical signal using an optical detector provided on the second substrate, and converting the received optical signal to an electrical signal. Accordingly, using a mid-infrared wavelength range of light that is transparent to semiconductor materials such as silicon and next-generation high-mobility materials, it is possible to enable interconnection between stacked semiconductor chips without using metal wiring. Using optical interconnection, it is possible to significantly reduce the bandwidth and power consumption, and overcome the limitations of TSV technology, and it is possible to extend the photonics technology and platform established in the existing Si Photonics, thereby reducing the cost required for design.

公开(公告)号：US20190287846A1

公开(公告)日：2019-09-19

申请号：US16282299

申请日：2019-02-22

Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Hyung-jun KIM ,  Sanghyeon KIM ,  Hansung KIM ,  Seong Kwang KIM ,  Hyeong Rak LIM

IPC: H01L21/762 ,  H01L21/683 ,  H01L21/02 ,  H01L21/78 ,  H01L29/06

Abstract: A method for manufacturing a semiconductor device according to embodiments may include forming a sacrificial layer on a first substrate including first dopant atoms and second dopant atoms, and forming a germanium (Ge) layer on the sacrificial layer. Here, the germanium (Ge) layer may include the first dopant atoms diffused from the first substrate by growth temperature in the forming step. Additionally, the method for manufacturing a semiconductor device may further include annealing after growth of the germanium (Ge) layer so that the germanium (Ge) layer may include second dopant atoms.

公开(公告)号：US20160343810A1

公开(公告)日：2016-11-24

申请号：US14854221

申请日：2015-09-15

Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Sanghyeon KIM ,  Daemyeong GEUM ,  Min Su PARK ,  Won Jun CHOI

IPC: H01L29/205 ,  H01L21/78 ,  H01L29/165 ,  H01L21/683 ,  H01L21/18

CPC classification number: H01L21/78 ,  H01L21/185 ,  H01L21/6835 ,  H01L29/267 ,  H01L29/66219 ,  H01L29/861 ,  H01L31/0304 ,  H01L31/184 ,  H01L31/1892 ,  Y02E10/544

Abstract: Disclosed is a method for manufacturing a semiconductor device, which includes providing a template having a first substrate and a patterned first III-V group compound layer located on the first substrate, forming a sacrificial layer on the patterned first III-V group compound layer by epitaxial growth, forming a second III-V group compound layer on the sacrificial layer by epitaxial growth, bonding a second substrate made of silicon onto the second III-V group compound layer, and separating the second III-V group compound layer and the second substrate from the template by removing the sacrificial layer.

Abstract translation: 公开了一种制造半导体器件的方法，其包括提供具有第一衬底和位于第一衬底上的图案化的第一III-V族化合物层的模板，在图案化的第一III-V族化合物层上形成牺牲层， 外延生长，通过外延生长在牺牲层上形成第二III-V族化合物层，将由硅制成的第二衬底接合到第二III-V族化合物层上，以及将第二III-V族化合物层和第二III-V族化合物层分离 通过去除牺牲层从模板的衬底。