公开(公告)号：US20100169616A1

公开(公告)日：2010-07-01

申请号：US12631098

申请日：2009-12-04

申请人： Kai-Feng WANG ,  Hong-Xia Sun ,  Peng-fei Zhu ,  Yong-qiang Wu

发明人： Kai-Feng WANG ,  Hong-Xia Sun ,  Peng-fei Zhu ,  Yong-qiang Wu

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/3855

摘要： An embodiment of a technique for selecting instructions for execution from an issue queue at multiple function units while reducing the chances of instruction collisions. Each function unit in a processor may include a selection logic circuit that selects a specific instruction from the issue queue for execution. In order to avoid instruction collision, a function unit may have a selection logic circuit that may select two instructions from an instruction queue: one according to a first selection technique and one according to a second selection technique. Then, by comparing the instruction selected by the first selection technique to the instruction selected by the selection logic circuit of another function unit, the instruction selected by the second technique may be used instead if there will be an instruction collision because the instruction selected by the first selection technique is the same as the instruction selected at a different function unit.

摘要翻译： 一种用于在减少指令冲突的机会的同时从多个功能单元的发布队列中选择用于执行的指令的技术的实施例。 处理器中的每个功能单元可以包括选择逻辑电路，其从发布队列中选择特定指令以供执行。 为了避免指令冲突，功能单元可以具有可以从指令队列中选择两个指令的选择逻辑电路：根据第一选择技术和第二选择技术的选择逻辑电路。 然后，通过将由第一选择技术选择的指令与由另一功能单元的选择逻辑电路选择的指令进行比较，可以使用由第二技术选择的指令来代替，否则将产生指令冲突，因为由 第一选择技术与在不同功能单元处选择的指令相同。

公开(公告)号：US20100169626A1

公开(公告)日：2010-07-01

申请号：US12615108

申请日：2009-11-09

申请人： Kai-Feng WANG ,  Hong-Xia Sun

发明人： Kai-Feng WANG ,  Hong-Xia Sun

IPC分类号： G06F9/38

CPC分类号： G06F9/3806 ,  G06F9/3848

摘要： A system and method for predicting the execution of a branch of computer-executable instructions. In an embodiment, a branch predictor may include a program-counter register operable to store a program-counter value and a branch-history register operable to store a branch-history value. Additionally, the branch predictor may include a prediction hash table having a plurality of prediction values each uniquely corresponding to a plurality of memory locations. With these components, the branch predictor may generate a first prediction value that corresponds to the program-counter value and may generate a second prediction value that corresponds to a logical combination of the program-counter value and the branch-history value. With these two prediction values obtained from two different prediction schemas, the branch predictor is better suited to generate an overall prediction value based on the first and second prediction values that is more accurate than a single prediction value based upon a single prediction schema.

摘要翻译： 一种用于预测计算机可执行指令的分支的执行的系统和方法。 在一个实施例中，分支预测器可以包括可操作以存储程序计数器值的程序计数器寄存器和可操作以存储分支历史值的分支历史寄存器。 另外，分支预测器可以包括具有唯一对应于多个存储器位置的多个预测值的预测散列表。 利用这些组件，分支预测器可以产生对应于程序计数器值的第一预测值，并且可以生成对应于程序计数器值和分支历史值的逻辑组合的第二预测值。 利用从两个不同的预测模式获得的这两个预测值，分支预测器更适合于基于基于单个预测模式的单个预测值更准确的第一和第二预测值来生成总体预测值。