Reliable packet delivery with overlay network (RPDON)
    1.
    发明授权
    Reliable packet delivery with overlay network (RPDON) 有权
    覆盖网络可靠的分组传输(RPDON)

    公开(公告)号:US09391878B2

    公开(公告)日:2016-07-12

    申请号:US13358130

    申请日:2012-01-25

    摘要: In one embodiment, a device in a computer network establishes a reliable map that defines a set of packet criteria for which reliability is desired over an unreliable link to a peer device. In response to receiving a first packet from the peer device over the unreliable link, the device acknowledges the first packet to the peer device when the first packet matches the packet criteria of the reliable map. Also, in response to receiving a second packet destined via the peer device over the unreliable link, the device buffers the second packet when the second packet matches the packet criteria of the reliable map and retransmits the buffered second packet over the unreliable link to the peer device until acknowledged by the peer device.

    摘要翻译: 在一个实施例中,计算机网络中的设备建立可靠的映射,其定义了通过对对等设备的不可靠链路来期望可靠性的一组分组标准。 响应于通过不可靠链路从对等设备接收到第一分组,当第一分组匹配可靠地图的分组标准时,设备向对等设备确认第一分组。 此外,响应于通过不可靠链路接收经由对等设备发送的第二分组,当第二分组与可靠映射的分组标准匹配时,设备缓冲第二分组,并且经由不可靠链路将对缓冲的第二分组重传到对等体 设备,直到对等设备确认。

    RELIABLE PACKET DELIVERY WITH OVERLAY NETWORK (RPDON)
    2.
    发明申请
    RELIABLE PACKET DELIVERY WITH OVERLAY NETWORK (RPDON) 有权
    可靠的分组交付与覆盖网络(RPDON)

    公开(公告)号:US20130188471A1

    公开(公告)日:2013-07-25

    申请号:US13358130

    申请日:2012-01-25

    IPC分类号: H04L12/24

    摘要: In one embodiment, a device in a computer network establishes a reliable map that defines a set of packet criteria for which reliability is desired over an unreliable link to a peer device. In response to receiving a first packet from the peer device over the unreliable link, the device acknowledges the first packet to the peer device when the first packet matches the packet criteria of the reliable map. Also, in response to receiving a second packet destined via the peer device over the unreliable link, the device buffers the second packet when the second packet matches the packet criteria of the reliable map and retransmits the buffered second packet over the unreliable link to the peer device until acknowledged by the peer device.

    摘要翻译: 在一个实施例中,计算机网络中的设备建立可靠的映射,其定义了通过对对等设备的不可靠链路来期望可靠性的一组分组标准。 响应于通过不可靠链路从对等设备接收到第一分组,当第一分组匹配可靠地图的分组标准时,设备向对等设备确认第一分组。 此外,响应于通过不可靠链路接收经由对等设备发送的第二分组,当第二分组与可靠映射的分组标准匹配时,设备缓冲第二分组,并且经由不可靠链路将对缓冲的第二分组重传到对等体 设备,直到对等设备确认。

    Reduced authentication times for shared-media network migration
    3.
    发明授权
    Reduced authentication times for shared-media network migration 有权
    降低了共享媒体网络迁移的验证时间

    公开(公告)号:US08949959B2

    公开(公告)日:2015-02-03

    申请号:US13400991

    申请日:2012-02-21

    IPC分类号: H04L29/00

    摘要: In one embodiment, a management device in a computer network determines when nodes of the computer network join any one of a plurality of field area routers (FARs), which requires a shared-media mesh security key for that joined FAR. The management device also maintains a database that indicates to which FAR each node in the computer network is currently joined, and to which FARs, if any, each node had previously joined, where the nodes are configured to maintain the mesh security key for one or more previously joined FARs in order to return to those previously joined FARs with the maintained mesh security key. Accordingly, in response to an updated mesh security key for a particular FAR of the plurality of FARs, the management node initiates distribution of the updated mesh security key to nodes having previously joined that particular FAR that are not currently joined to that particular FAR.

    摘要翻译: 在一个实施例中,计算机网络中的管理设备确定计算机网络的何时节点连接多个场区域路由器(FAR)中的任何一个,其需要用于该加入的FAR的共享 - 媒体网状安全密钥。 管理设备还维护一个数据库,指示计算机网络中每个节点当前加入哪个FAR,以及每个节点先前已加入的哪个FAR(如果有的话),其中节点被配置为维护一个或多个节点的网状安全密钥 以前加入的FAR,以便返回到以前加入的FAR与维护的网状安全密钥。 因此,响应于针对多个FAR的特定FAR的更新的网状安全密钥,管理节点发起更新的网状安全密钥到先前已加入到当前未连接到该特定FAR的特定FAR的节点的分发。

    REDUCED AUTHENTICATION TIMES FOR SHARED-MEDIA NETWORK MIGRATION
    4.
    发明申请
    REDUCED AUTHENTICATION TIMES FOR SHARED-MEDIA NETWORK MIGRATION 有权
    减少媒体网络移动的认证时间

    公开(公告)号:US20130219478A1

    公开(公告)日:2013-08-22

    申请号:US13400991

    申请日:2012-02-21

    IPC分类号: G06F21/20

    摘要: In one embodiment, a management device in a computer network determines when nodes of the computer network join any one of a plurality of field area routers (FARs), which requires a shared-media mesh security key for that joined FAR. The management device also maintains a database that indicates to which FAR each node in the computer network is currently joined, and to which FARs, if any, each node had previously joined, where the nodes are configured to maintain the mesh security key for one or more previously joined FARs in order to return to those previously joined FARs with the maintained mesh security key. Accordingly, in response to an updated mesh security key for a particular FAR of the plurality of FARs, the management node initiates distribution of the updated mesh security key to nodes having previously joined that particular FAR that are not currently joined to that particular FAR.

    摘要翻译: 在一个实施例中,计算机网络中的管理设备确定计算机网络的何时节点连接多个场区域路由器(FAR)中的任何一个,其需要该加入的FAR的共享媒体网状安全密钥。 管理设备还维护一个数据库,指示计算机网络中每个节点当前加入哪个FAR,以及每个节点先前已加入的哪个FAR(如果有的话),其中节点被配置为维护一个或多个节点的网状安全密钥 以前加入的FAR,以便返回到以前加入的FAR与维护的网状安全密钥。 因此,响应于针对多个FAR的特定FAR的更新的网状安全密钥,管理节点发起更新的网状安全密钥到先前已加入到当前未连接到该特定FAR的特定FAR的节点的分发。

    Fully differential, high Q, on-chip, impedance matching section
    5.
    发明授权
    Fully differential, high Q, on-chip, impedance matching section 有权
    全差分,高Q,片上,阻抗匹配部分

    公开(公告)号:US08274353B2

    公开(公告)日:2012-09-25

    申请号:US13047699

    申请日:2011-03-14

    IPC分类号: H01F5/00

    摘要: An inductor circuit is disclosed. The inductor circuit includes a first in-silicon inductor and a second in-silicon inductor each having multiple turns. A portion of the multiple turns of the second in-silicon inductor is formed between turns of the first in-silicon inductor. The first and second in-silicon inductors are configured such that a differential current flowing through the first in-silicon inductor and the second in-silicon inductor flows in a same direction in corresponding turns of inductors.

    摘要翻译: 公开了一种电感器电路。 电感器电路包括第一硅芯片电感器和第二硅芯片电感器,每个具有多个匝数。 第二硅电感器的多圈的一部分形成在第一硅内感应器的匝之间。 第一和第二硅内电感器被配置为使得流过第一硅芯片电感器和第二硅芯片电感器的差分电流在相应的电感圈中以相同的方向流动。

    Fully Differential, High Q, On-Chip, Impedance Matching Section
    6.
    发明申请
    Fully Differential, High Q, On-Chip, Impedance Matching Section 失效
    全差分,高Q,片上,阻抗匹配部分

    公开(公告)号:US20090127654A1

    公开(公告)日:2009-05-21

    申请号:US12360068

    申请日:2009-01-26

    IPC分类号: H01L27/02

    摘要: An inductor circuit is disclosed. The inductor circuit includes a first in-silicon inductor and a second in-silicon inductor each having multiple turns. A portion of the multiple turns of the second in-silicon inductor is formed between turns of the first in-silicon inductor. The first and second in-silicon inductors are configured such that a differential current flowing through the first in-silicon inductor and the second in-silicon inductor flows in a same direction in corresponding turns of inductors.

    摘要翻译: 公开了一种电感器电路。 电感器电路包括第一硅芯片电感器和第二硅芯片电感器,每个具有多个匝数。 第二硅电感器的多圈的一部分形成在第一硅内感应器的匝之间。 第一和第二硅内电感器被配置为使得流过第一硅芯片电感器和第二硅芯片电感器的差分电流在相应的电感圈中以相同的方向流动。

    Fully differential, high Q, on-chip, impedance matching section
    7.
    发明授权
    Fully differential, high Q, on-chip, impedance matching section 有权
    全差分,高Q,片上,阻抗匹配部分

    公开(公告)号:US07489221B2

    公开(公告)日:2009-02-10

    申请号:US11504073

    申请日:2006-08-15

    IPC分类号: H01F5/00

    摘要: An inductor circuit is disclosed. The inductor circuit includes a first in-silicon inductor and a second in-silicon inductor each having multiple turns. A portion of the multiple turns of the second in-silicon inductor is formed between turns of the first in-silicon inductor. The first and second in-silicon inductors are configured such that a differential current flowing through the first in-silicon inductor and the second in-silicon inductor flows in a same direction in corresponding turns of inductors.

    摘要翻译: 公开了一种电感器电路。 电感器电路包括第一硅芯片电感器和第二硅芯片电感器,每个具有多个匝数。 第二硅电感器的多圈的一部分形成在第一硅内感应器的匝之间。 第一和第二硅内电感器被配置为使得流过第一硅芯片电感器和第二硅芯片电感器的差分电流在相应的电感圈中以相同的方向流动。

    Fully differential, high Q, on-chip, impedance matching section
    8.
    发明授权
    Fully differential, high Q, on-chip, impedance matching section 失效
    全差分,高Q,片上,阻抗匹配部分

    公开(公告)号:US07911310B2

    公开(公告)日:2011-03-22

    申请号:US12360068

    申请日:2009-01-26

    IPC分类号: H01F5/00

    摘要: An inductor circuit is disclosed. The inductor circuit includes a first in-silicon inductor and a second in-silicon inductor each having multiple turns. A portion of the multiple turns of the second in-silicon inductor is formed between turns of the first in-silicon inductor. The first and second in-silicon inductors are configured such that a differential current flowing through the first in-silicon inductor and the second in-silicon inductor flows in a same direction in corresponding turns of inductors.

    摘要翻译: 公开了一种电感器电路。 电感器电路包括第一硅芯片电感器和第二硅芯片电感器,每个具有多个匝数。 第二硅电感器的多圈的一部分形成在第一硅内感应器的匝之间。 第一和第二硅内电感器被配置为使得流过第一硅芯片电感器和第二硅芯片电感器的差分电流在相应的电感圈中以相同的方向流动。

    Fully Differential, High Q, On-Chip, Impedance Matching Section
    9.
    发明申请
    Fully Differential, High Q, On-Chip, Impedance Matching Section 有权
    全差分,高Q,片上,阻抗匹配部分

    公开(公告)号:US20110163831A1

    公开(公告)日:2011-07-07

    申请号:US13047699

    申请日:2011-03-14

    IPC分类号: H01F5/00

    摘要: An inductor circuit is disclosed. The inductor circuit includes a first in-silicon inductor and a second in-silicon inductor each having multiple turns. A portion of the multiple turns of the second in-silicon inductor is formed between turns of the first in-silicon inductor. The first and second in-silicon inductors are configured such that a differential current flowing through the first in-silicon inductor and the second in-silicon inductor flows in a same direction in corresponding turns of inductors.

    摘要翻译: 公开了一种电感器电路。 电感器电路包括第一硅芯片电感器和第二硅芯片电感器,每个具有多个匝数。 第二硅电感器的多圈的一部分形成在第一硅内感应器的匝之间。 第一和第二硅内电感器被配置为使得流过第一硅芯片电感器和第二硅芯片电感器的差分电流在相应的电感圈中以相同的方向流动。