公开(公告)号：US06363112B1

公开(公告)日：2002-03-26

申请号：US09206527

申请日：1998-12-07

Applicant: Kameran Azadet ,  Ming-Lin Yu

Inventor： Kameran Azadet ,  Ming-Lin Yu

IPC: H03K5159

CPC classification number: H04L25/03057 ,  H04L2025/0349

Abstract: A parallel processing decision feedback equalizer is configured to receive a plurality of symbol blocks in parallel via a plurality of corresponding input branches. It is further configured to generate a plurality of decision samples. The equalizer comprises an input buffer for storing calculated decision samples corresponding to at least one previously received symbol block and a plurality of tapped delay calculators coupled to the input buffer and located in each of the input branches which are configured to calculate the first portion of a decision feedback signal corresponding to each input branch based on the impulse response samples and the decision samples stored in said input buffer. A plurality of look-ahead-processors located in each one of the input branches and is coupled to a corresponding one of the tapped delay calculators. Each look-ahead-processor has a depth equal to the sequence order of its corresponding branch so as to calculate all possible components of a decision feedback signal for the corresponding branch. A plurality of selectors are coupled to the look-ahead processors so as to select appropriate ones of the possible components of the decision feedback signal based on decision samples obtained from previous branches.

Abstract translation: 并行处理判决反馈均衡器被配置为经由多个对应的输入分支并行地接收多个符号块。 其还被配置为生成多个决策样本。 均衡器包括用于存储与至少一个先前接收的符号块相对应的计算出的决定样本的输入缓冲器和耦合到输入缓冲器并位于每个输入分支中的多个抽头延迟计算器，其被配置为计算第一部分 基于脉冲响应样本和存储在所述输入缓冲器中的判定样本，对应于每个输入分支的判决反馈信号。多个前视处理器，位于每个输入分支中，并且耦合到相应的一个被敲击 延迟计算器。 每个先行处理器的深度等于其相应分支的序列顺序，以便计算相应分支的判定反馈信号的所有可能分量。 多个选择器被耦合到先行处理器，以便基于从先前分支获得的判定样本来选择判定反馈信号的可能分量中的适当的选择器。