Equalizing a transmitter
    1.
    发明授权
    Equalizing a transmitter 有权
    变送器均衡

    公开(公告)号:US07596174B2

    公开(公告)日:2009-09-29

    申请号:US11237118

    申请日:2005-09-28

    IPC分类号: H04B7/30

    摘要: In one embodiment, the present invention includes a method for associating a first plurality of current sources with a first tap coefficient and associating a second plurality of current sources with a second tap coefficient. A first plurality of output switches coupled to the first plurality of current sources is gated using the first tap coefficient and a second plurality of output switches coupled to the second plurality of current sources is gated using the second tap coefficient. In such manner, the first and second plurality of equalized current sources may be driven onto an interconnect. Other embodiments are described and claimed.

    摘要翻译: 在一个实施例中,本发明包括用于将第一多个电流源与第一抽头系数相关联并将第二多个电流源与第二抽头系数相关联的方法。 耦合到第一多个电流源的第一多个输出开关使用第一抽头系数进行门控,并且使用第二抽头系数选择耦合到第二多个电流源的第二多个输出开关。 以这种方式,第一和第二多个均衡的电流源可以被驱动到互连上。 描述和要求保护其他实施例。

    I/O link with configurable forwarded and derived clocks
    2.
    发明授权
    I/O link with configurable forwarded and derived clocks 有权
    I / O链接与可配置的转发和派生时钟

    公开(公告)号:US08315347B2

    公开(公告)日:2012-11-20

    申请号:US12592705

    申请日:2009-12-01

    IPC分类号: H04L7/02

    摘要: An electronic communications receiver includes a derived clock signal circuit operable to receive a data signal and to derive a derived clock signal from the received data signal. A separate forwarded clock signal circuit is further operable to receive a forwarded clock signal, and a clock management circuit is operable to receive signals from the derived clock signal circuit and the forwarded clock signal circuit, and to output an output clock signal.

    摘要翻译: 电子通信接收机包括导出的时钟信号电路,其可操作以接收数据信号并从接收的数据信号导出导出的时钟信号。 单独转发的时钟信号电路还可操作以接收转发的时钟信号,并且时钟管理电路可操作以从导出的时钟信号电路和转发的时钟信号电路接收信号,并输出输出时钟信号。

    I/O Link with configurable forwarded and derived clocks
    4.
    发明申请
    I/O Link with configurable forwarded and derived clocks 有权
    I / O链路与可配置的转发和派生时钟

    公开(公告)号:US20100098201A1

    公开(公告)日:2010-04-22

    申请号:US12592705

    申请日:2009-12-01

    IPC分类号: H04L7/00

    摘要: An electronic communications receiver includes a derived clock signal circuit operable to receive a data signal and to derive a derived clock signal from the received data signal. A separate forwarded clock signal circuit is further operable to receive a forwarded clock signal, and a clock management circuit is operable to receive signals from the derived clock signal circuit and the forwarded clock signal circuit, and to output an output clock signal.

    摘要翻译: 电子通信接收机包括导出的时钟信号电路,其可操作以接收数据信号并从接收的数据信号导出导出的时钟信号。 单独转发的时钟信号电路还可操作以接收转发的时钟信号,并且时钟管理电路可操作以从导出的时钟信号电路和转发的时钟信号电路接收信号,并输出输出时钟信号。

    I/O link with configurable forwarded and derived clocks
    5.
    发明授权
    I/O link with configurable forwarded and derived clocks 有权
    I / O链接与可配置的转发和派生时钟

    公开(公告)号:US07636411B2

    公开(公告)日:2009-12-22

    申请号:US10610316

    申请日:2003-06-30

    IPC分类号: H04L7/00

    摘要: An electronic communications receiver includes a derived clock signal circuit operable to receive a data signal and to derive a derived clock signal from the received data signal. A separate forwarded clock signal circuit is further operable to receive a forwarded clock signal, and a clock management circuit is operable to receive signals from the derived clock signal circuit and the forwarded clock signal circuit, and to output an output clock signal.

    摘要翻译: 电子通信接收机包括导出的时钟信号电路,其可操作以接收数据信号并从接收的数据信号导出导出的时钟信号。 单独转发的时钟信号电路还可操作以接收转发的时钟信号,并且时钟管理电路可操作以从导出的时钟信号电路和转发的时钟信号电路接收信号,并输出输出时钟信号。