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公开(公告)号：US20090096438A1
公开(公告)日：2009-04-16
申请号：US12236556
申请日：2008-09-24
IPC分类号： G05F3/20
CPC分类号： G05F1/567
摘要： A voltage control circuit accepts an input voltage and produces a regulated output voltage. Embodiments provide improved responsiveness to variations in input voltage, load current, and ambient temperature. Exemplary embodiments include an NPN transistor connected between the input and output terminals, which is controlled by a feedback circuit. In an embodiment, the feedback circuit includes a PMOS transistor and in another embodiment the feedback circuit includes a PNP transistor.
摘要翻译： 电压控制电路接受输入电压并产生稳定的输出电压。 实施例提供对输入电压，负载电流和环境温度变化的响应性的改善。 示例性实施例包括连接在由反馈电路控制的输入和输出端子之间的NPN晶体管。 在一个实施例中，反馈电路包括PMOS晶体管，在另一个实施例中，反馈电路包括PNP晶体管。
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公开(公告)号：US08013582B2
公开(公告)日：2011-09-06
申请号：US12236556
申请日：2008-09-24
CPC分类号： G05F1/567
摘要： A voltage control circuit accepts an input voltage and produces a regulated output voltage. Embodiments provide improved responsiveness to variations in input voltage, load current, and ambient temperature. Exemplary embodiments include an NPN transistor connected between the input and output terminals, which is controlled by a feedback circuit. In an embodiment, the feedback circuit includes a PMOS transistor and in another embodiment the feedback circuit includes a PNP transistor.
摘要翻译： 电压控制电路接受输入电压并产生稳定的输出电压。 实施例提供对输入电压，负载电流和环境温度变化的响应性的改善。 示例性实施例包括连接在由反馈电路控制的输入和输出端子之间的NPN晶体管。 在一个实施例中，反馈电路包括PMOS晶体管，在另一个实施例中，反馈电路包括PNP晶体管。
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公开(公告)号：US06940316B2
公开(公告)日：2005-09-06
申请号：US10807184
申请日：2004-03-24
CPC分类号： H03K5/2481 , H03K3/35613 , H03K3/356191 , H03K5/249
摘要： In order to provide a comparator circuit without generating a malfunction, the comparator circuit according to the present invention may comprise a comparator circuit including a differential amplification circuit having a differential pair transistor (M1, M2) for inputting a signal as an object of comparison, and a current mirror load circuit (M3, M4, M5, M6); a latch circuit having inversion amplifiers that are configured so that an input of one amplifier becomes an input of other amplifier so as to amplify a differential output signal outputted from the current mirror load circuit in accordance with a magnitude relation of the signal as an object of comparison; an equalization transistor (M9) for equalizing a signal of the differential amplification circuit; a delay circuit (M13, M14,M15, M16) for generating a signal to delay a control signal to be inputted in a control electrode of the equalization transistor; and a control transistor (M10) for inputting an output signal of the delay circuit in the control electrode as a control signal to make the latch circuit into an active status and a non-active status.
摘要翻译： 为了提供比较器电路而不产生故障，根据本发明的比较器电路可以包括比较器电路，其包括差分放大电路，差分放大电路具有用于输入作为对象的信号的差分对晶体管（M 1，M 2） 比较和电流反射镜负载电路（M 3，M 4，M 5，M 6）; 具有反相放大器的锁存电路，其被配置为使得一个放大器的输入变为其他放大器的输入，以便根据作为对象的信号的幅度关系放大从电流镜载入电路输出的差分输出信号 比较; 均衡晶体管（M 9），用于均衡差分放大电路的信号; 用于产生延迟要输入到均衡晶体管的控制电极的控制信号的信号的延迟电路（M13，M14，M15，M16）; 以及控制晶体管（M10），用于输入控制电极中的延迟电路的输出信号作为控制信号，以使锁存电路处于活动状态和非活动状态。
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公开(公告)号：US20050104626A1
公开(公告)日：2005-05-19
申请号：US10807184
申请日：2004-03-24
CPC分类号： H03K5/2481 , H03K3/35613 , H03K3/356191 , H03K5/249
摘要： In order to provide a comparator circuit without generating a malfunction, the comparator circuit according to the present invention may comprise a comparator circuit including a differential amplification circuit having a differential pair transistor (M1, M2) for inputting a signal as an object of comparison, and a current mirror load circuit (M3, M4, M5, M6); a latch circuit having inversion amplifiers that are configured so that an input of one amplifier becomes an input of other amplifier so as to amplify a differential output signal outputted from the current mirror load circuit in accordance with a magnitude relation of the signal as an object of comparison; an equalization transistor (M9) for equalizing a signal of the differential amplification circuit; a delay circuit (M13, M14,M15, M16) for generating a signal to delay a control signal to be inputted in a control electrode of the equalization transistor; and a control transistor (M10) for inputting an output signal of the delay circuit in the control electrode as a control signal to make the latch circuit into an active status and a non-active status.
摘要翻译： 为了提供比较器电路而不产生故障，根据本发明的比较器电路可以包括比较器电路，其包括差分放大电路，差分放大电路具有用于输入作为对象的信号的差分对晶体管（M 1，M 2） 比较和电流反射镜负载电路（M 3，M 4，M 5，M 6）; 具有反相放大器的锁存电路，其被配置为使得一个放大器的输入变为其他放大器的输入，以便根据作为对象的信号的幅度关系放大从电流镜载入电路输出的差分输出信号 比较; 均衡晶体管（M 9），用于均衡差分放大电路的信号; 用于产生延迟要输入到均衡晶体管的控制电极的控制信号的信号的延迟电路（M13，M14，M15，M16）; 以及控制晶体管（M10），用于输入控制电极中的延迟电路的输出信号作为控制信号，以使锁存电路处于活动状态和非活动状态。
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公开(公告)号：US5424855A
公开(公告)日：1995-06-13
申请号：US238839
申请日：1994-05-04
申请人： Yukio Nakamura , Kazuo Tokura , Shigemitsu Horikawa , Tokio Sato
发明人： Yukio Nakamura , Kazuo Tokura , Shigemitsu Horikawa , Tokio Sato
CPC分类号： H04N1/02418 , H04N1/024 , H04N1/40031 , H04N1/40056
摘要： An array of LEDs is controlled by a control circuit so as to emit light in a write mode and sense light in a read mode. In the read mode, each LED is alternately charged for a first interval, then allowed to discharge by flow of photocurrent for a second interval. At the end of the second interval, just before charging of the LED begins again, the anode voltage of the LED is read by coupling the anode of the LED to an output terminal for a third interval. The third interval of each LED may coincide with the first interval of the preceding LED in tile array, so that each LED is read while the preceding LED is being charged.
摘要翻译： LED阵列由控制电路控制，以便以写模式发光，并以读模式感测光。 在读取模式下，每个LED交替地充电一个第一间隔，然后允许通过光电流的流动放电一段间隔。 在第二间隔结束时，在LED再次开始充电之前，LED的阳极电压通过将LED的阳极耦合到输出端来读取第三间隔。 每个LED的第三间隔可以与瓦片阵列中的先前LED的第一间隔重合，使得在前面的LED被充电的同时读取每个LED。
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