公开(公告)号：US20080104365A1

公开(公告)日：2008-05-01

申请号：US11957781

申请日：2007-12-17

申请人： Kazuhyoshi Kohno ,  Atsushi Mizuno ,  Atsushi Masuda ,  Ryuichiro Ohyama ,  Yutaka Ota

发明人： Kazuhyoshi Kohno ,  Atsushi Mizuno ,  Atsushi Masuda ,  Ryuichiro Ohyama ,  Yutaka Ota

IPC分类号： G06F15/00

CPC分类号： G06F17/5045 ,  G06F8/4434 ,  G06F17/5022

摘要： A design apparatus for designing a processor re-configurable for an application, includes an analysis unit that analyzes the content of a program to be executed by the processor; a hardware extension unit that searches the program for a part of the program allowing hardware extension in accordance with the analysis results by the analysis unit and generates hardware extension information for the searched part; an extended instruction definition unit that searches the program for a part allowing use of an extended instruction in accordance with the analysis results by the analysis unit and generates definition of an extended instruction for the searched part; and a performance estimation unit that estimates whether or not the performance of the processor satisfies a target performance using at least one of the hardware extension information generated by the hardware extension unit and the definition of the extended instruction generated by the extended instruction definition unit.

摘要翻译： 一种用于设计用于应用的可重配置的处理器的设计装置，包括：分析单元，分析由处理器执行的程序的内容; 硬件扩展单元，其根据分析单元的分析结果搜索程序的一部分，允许硬件扩展，并产生搜索到的部分的硬件扩展信息; 扩展指令定义单元，其根据分析单元的分析结果搜索程序中允许使用扩展指令的部分，并生成所搜索的部分的扩展指令的定义; 以及性能估计单元，其使用由所述硬件扩展单元生成的硬件扩展信息和由所述扩展指令定义单元生成的扩展指令的定义中的至少一个来估计所述处理器的性能是否满足目标性能。

公开(公告)号：US20050193184A1

公开(公告)日：2005-09-01

申请号：US11044085

申请日：2005-01-28

申请人： Kazuyoshi Kohno ,  Atsushi Mizuno ,  Atsushi Masuda ,  Ryuichiro Ohyama ,  Yutaka Ota

发明人： Kazuyoshi Kohno ,  Atsushi Mizuno ,  Atsushi Masuda ,  Ryuichiro Ohyama ,  Yutaka Ota

IPC分类号： G06F17/50 ,  G06F9/45 ,  G06F15/00

CPC分类号： G06F17/5045 ,  G06F8/4434 ,  G06F17/5022

摘要： A design apparatus for designing a configurable processor for an application, includes an analysis unit that analyzes the content of a program to be executed by the processor; a hardware extension unit that searches the program for a part of the program allowing hardware extension in accordance with the analysis results by the analysis unit and generates hardware extension information for the searched part; an extension instruction definition unit that searches the program for a part allowing use of an extension instruction in accordance with the analysis results by the analysis unit and generates definition of an extension instruction for the searched part; and a performance estimation unit that estimates whether or not the performance of the processor satisfies a target performance using at least one of the hardware extension information generated by the hardware extension unit and the definition of the extension instruction generated by the extension instruction definition unit.

摘要翻译： 一种用于设计用于应用的可配置处理器的设计装置，包括：分析单元，分析由处理器执行的程序的内容; 硬件扩展单元，其根据分析单元的分析结果搜索程序的一部分，允许硬件扩展，并产生搜索到的部分的硬件扩展信息; 扩展指令定义单元，其根据分析单元的分析结果搜索程序中允许使用扩展指令的部分，并生成所搜索的部分的扩展指令的定义; 以及性能估计单元，其使用由所述硬件扩展单元生成的硬件扩展信息和由所述扩展指令定义单元生成的所述扩展指令的定义中的至少一个来估计所述处理器的性能是否满足目标性能。

公开(公告)号：US07707386B2

公开(公告)日：2010-04-27

申请号：US11957781

申请日：2007-12-17

申请人： Kazuyoshi Kohno ,  Atsushi Mizuno ,  Atsushi Masuda ,  Ryuichiro Ohyama ,  Yutaka Ota

发明人： Kazuyoshi Kohno ,  Atsushi Mizuno ,  Atsushi Masuda ,  Ryuichiro Ohyama ,  Yutaka Ota

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F8/4434 ,  G06F17/5022

摘要： A design apparatus for designing a processor re-configurable for an application, includes an analysis unit that analyzes the content of a program to be executed by the processor; a hardware extension unit that searches the program for a part of the program allowing hardware extension in accordance with the analysis results by the analysis unit and generates hardware extension information for the searched part; an extended instruction definition unit that searches the program for a part allowing use of an extended instruction in accordance with the analysis results by the analysis unit and generates definition of an extended instruction for the searched part; and a performance estimation unit that estimates whether or not the performance of the processor satisfies a target performance using at least one of the hardware extension information generated by the hardware extension unit and the definition of the extended instruction generated by the extended instruction definition unit.

摘要翻译： 一种用于设计用于应用的可重配置的处理器的设计装置，包括：分析单元，分析由处理器执行的程序的内容; 硬件扩展单元，其根据分析单元的分析结果搜索程序的一部分，允许硬件扩展，并产生搜索到的部分的硬件扩展信息; 扩展指令定义单元，其根据分析单元的分析结果搜索程序中允许使用扩展指令的部分，并生成所搜索的部分的扩展指令的定义; 以及性能估计单元，其使用由所述硬件扩展单元生成的硬件扩展信息和由所述扩展指令定义单元生成的扩展指令的定义中的至少一个来估计所述处理器的性能是否满足目标性能。

公开(公告)号：US07337301B2

公开(公告)日：2008-02-26

申请号：US11044085

申请日：2005-01-28

申请人： Kazuyoshi Kohno ,  Atsushi Mizuno ,  Atsushi Masuda ,  Ryuichiro Ohyama ,  Yutaka Ota

发明人： Kazuyoshi Kohno ,  Atsushi Mizuno ,  Atsushi Masuda ,  Ryuichiro Ohyama ,  Yutaka Ota

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F8/4434 ,  G06F17/5022

摘要： A design apparatus for designing a configurable processor for an application, includes an analysis unit that analyzes the content of a program to be executed by the processor; a hardware extension unit that searches the program for a part of the program allowing hardware extension in accordance with the analysis results by the analysis unit and generates hardware extension information for the searched part; an extension instruction definition unit that searches the program for a part allowing use of an extension instruction in accordance with the analysis results by the analysis unit and generates definition of an extension instruction for the searched part; and a performance estimation unit that estimates whether or not the performance of the processor satisfies a target performance using at least one of the hardware extension information generated by the hardware extension unit and the definition of the extension instruction generated by the extension instruction definition unit.

摘要翻译： 一种用于设计用于应用的可配置处理器的设计装置，包括：分析单元，分析由处理器执行的程序的内容; 硬件扩展单元，其根据分析单元的分析结果搜索程序的一部分，允许硬件扩展，并产生搜索到的部分的硬件扩展信息; 扩展指令定义单元，其根据分析单元的分析结果搜索程序中允许使用扩展指令的部分，并生成所搜索的部分的扩展指令的定义; 以及性能估计单元，其使用由所述硬件扩展单元生成的硬件扩展信息和由所述扩展指令定义单元生成的所述扩展指令的定义中的至少一个来估计所述处理器的性能是否满足目标性能。

公开(公告)号：US07917899B2

公开(公告)日：2011-03-29

申请号：US11362728

申请日：2006-02-28

申请人： Yutaka Ota ,  Atsushi Mizuno

发明人： Yutaka Ota ,  Atsushi Mizuno

IPC分类号： G06F9/45

CPC分类号： G06F8/73 ,  G06F8/443

摘要： A program development apparatus includes a storage device configured to store an operation definition defining a program description in a source program subjected to be optimized and a complex intrinsic function including an inline clause describing statements after the optimization. An analyzer is configured to perform a syntax analysis of the complex intrinsic function by reading the complex intrinsic function out of the storage device, so as to detect the operation definition and the inline clause. A code generator is configured to generate an object code from the source program by optimizing a program description corresponding to the operation definition in the source program into the statements in the inline clause.

摘要翻译： 程序开发装置包括存储装置，其被配置为存储定义被优化的源程序中的程序描述的操作定义和包括在优化之后描述语句的内联子句的复数内在函数。 分析器被配置为通过从存储设备读出复杂的内在函数来执行复杂内在函数的语法分析，以便检测操作定义和内联子句。 代码生成器被配置为通过将源程序中的操作定义相对应的程序描述优化为内联子句中的语句来从源程序生成目标代码。

公开(公告)号：US20060200796A1

公开(公告)日：2006-09-07

申请号：US11362728

申请日：2006-02-28

申请人： Yutaka Ota ,  Atsushi Mizuno

发明人： Yutaka Ota ,  Atsushi Mizuno

IPC分类号： G06F9/44 ,  G06F9/45

CPC分类号： G06F8/73 ,  G06F8/443

摘要： A program development apparatus includes a storage device configured to store an operation definition defining a program description in a source program subjected to be optimized and a complex intrinsic function including an inline clause describing statements after the optimization. An analyzer is configured to perform a syntax analysis of the complex intrinsic function by reading the complex intrinsic function out of the storage device, so as to detect the operation definition and the inline clause. A code generator is configured to generate an object code from the source program by optimizing a program description corresponding to the operation definition in the source program into the statements in the inline clause.

摘要翻译： 程序开发装置包括存储装置，其被配置为存储定义被优化的源程序中的程序描述的操作定义和包括在优化之后描述语句的内联子句的复数内在函数。 分析器被配置为通过从存储设备读出复杂的内在函数来执行复杂内在函数的语法分析，以便检测操作定义和内联子句。 代码生成器被配置为通过将源程序中的操作定义相对应的程序描述优化为内联子句中的语句来从源程序生成目标代码。

公开(公告)号：US08888296B2

公开(公告)日：2014-11-18

申请号：US13421540

申请日：2012-03-15

申请人： Yutaka Ota ,  Ryuji Hada

发明人： Yutaka Ota ,  Ryuji Hada

IPC分类号： G03B21/14 ,  G09G3/00 ,  G06T1/20 ,  H04N9/31 ,  G09G5/39 ,  G06T1/60

CPC分类号： G03B21/147 ,  G06T1/20 ,  G06T1/60 ,  G09G3/002 ,  G09G5/39 ,  G09G2340/04 ,  H04N9/312 ,  H04N9/3179 ,  H04N9/3185 ,  H04N9/3188

摘要： A projector is provided with: an input line memory which holds an input image signal corresponding to one line; an image processor which generates an intermediate image signal correction-processed according to distortion of a projection lens, using the input image signal transferred from the input line memory; an output line memory which holds the intermediate image signal corresponding to one line; and an LCOS which guides light radiated from a light source to the projection lens in accordance with the intermediate image signal. The image processor is provided with an input supplementation buffer which stores the input image signals of a plurality of lines, an input data buffer which stores input image signals required to generate the intermediate image signal corresponding to one line, and a number-of-supplementary-lines calculator which calculates the number of supplementary lines of the input image signals.

摘要翻译： 投影仪具有：保持对应于一行的输入图像信号的输入行存储器; 图像处理器，使用从输入行存储器传送的输入图像信号，生成根据投影透镜的失真进行了校正处理的中间图像信号; 保持对应于一行的中间图像信号的输出行存储器; 以及根据中间图像信号将从光源照射的光引导到投影透镜的LCOS。 图像处理器设置有存储多条线的输入图像信号的输入补充缓冲器，存储生成对应于一行的中间图像信号所需的输入图像信号的输入数据缓冲器，以及补充数量 线计算器，其计算输入图像信号的补充行数。

公开(公告)号：US08476641B2

公开(公告)日：2013-07-02

申请号：US12745133

申请日：2008-09-08

申请人： Yoshiyuki Suda ,  Yutaka Ota

发明人： Yoshiyuki Suda ,  Yutaka Ota

IPC分类号： H01L29/24

CPC分类号： H01L27/101 ,  G11C13/0002 ,  G11C2213/72 ,  H01L21/8213 ,  H01L27/1021 ,  H01L27/1022 ,  H01L27/24

摘要： A switching resistance RAM that is highly integrated as well as reduced in a read-out time is realized. There is formed an NPN type bipolar transistor BT composed of a collector layer made of an N-well 11, a base layer made of a P+ type Si layer 12A formed in a surface of the N-well 11, and an emitter layer made of an N+ type Si layer 15 formed in a surface of the P+ type Si layer 12A. Also, there are formed a word line WL0 electrically connected to the N+ type Si layer 15 and bit lines BL1-BL4 intersecting with the word line WL0. Also, there are formed a plurality of switching layers 14 formed on a surface of the P+ type Si layer 12A, each being electrically connected to corresponding each of the bit lines and switching between an ON state and an OFF state and an electric potential fixing line 19A to fix the P+ type Si layer 12A at a predetermined electric potential.

摘要翻译： 实现高集成度以及减少读出时间的开关电阻RAM。 形成由N阱11构成的集电极构成的NPN型双极晶体管BT，在N阱11的表面形成的由P +型Si层12A构成的基极层和由N阱11的表面形成的发射极层 形成在P +型Si层12A的表面上的N +型Si层15。 而且，形成与N +型Si层15电连接的字线WL0，与字线WL0相交的位线BL1〜BL4。 此外，形成在P +型Si层12A的表面上形成的多个开关层14，其各自与对应的每个位线电连接，并且在导通状态和断开状态之间切换以及电位固定线 19A以将P +型Si层12A固定在预定电位。

公开(公告)号：US20080285268A1

公开(公告)日：2008-11-20

申请号：US11667397

申请日：2005-10-24

申请人： Takashi Oku ,  Takeo Arai ,  Yutaka Ota ,  Yasuhiro Tagawa

发明人： Takashi Oku ,  Takeo Arai ,  Yutaka Ota ,  Yasuhiro Tagawa

IPC分类号： F21V9/00

CPC分类号： G02F1/133603 ,  G02F1/133608 ,  G02F1/133609 ,  G02F1/133611

摘要： Disclosed is a backlight device for illuminating a transmissive color liquid crystal display panel from its backside with white light. The backlight device includes, as a light source, a plural number of principal light emitting diode units 21mn, and a plural number of subsidiary light emitting diode units 21mn, where m and n are natural numbers. Each principal light emitting diode unit is made up by a plural number of light emitting diodes (21) arrayed in a string and emits white light of preset chromaticity. Each subsidiary light emitting diode unit is made up by a plural number of light emitting diodes (21) arrayed in a string and emits white light of chromaticity in the vicinity of the preset chromaticity. The number of the subsidiary light emitting diode units is smaller than that of the principal light emitting diode units. When the principal light emitting diode units and the subsidiary light emitting diode units are arrayed in a two-dimensional matrix, the subsidiary light emitting diode units 21mn are arrayed without being juxtaposed on the same row, and the subsidiary light emitting diode units 21mn, arrayed in a center column of the two-dimensional matrix, are arrayed towards the center of a color liquid crystal display panel (110).

摘要翻译： 公开了一种背光装置，其用白光从其背面照射透射彩色液晶显示面板。 背光装置包括多个主发光二极管单元21和多个辅助发光二极管单元21，作为光源，其中， m和n是自然数。 每个主要发光二极管单元由排列成串的多个发光二极管（21）构成并发出预定色度的白光。 每个辅助发光二极管单元由排列成串的多个发光二极管（21）构成，并且在预设色度附近发出色度的白光。 辅助发光二极管单元的数量小于主要发光二极管单元的数量。 当主发光二极管单元和辅助发光二极管单元排列成二维矩阵时，辅助发光二极管单元21排列而不并列在同一行上，并且 排列在二维矩阵的中心列中的辅助发光二极管单元21 朝向彩色液晶显示面板（110）的中心排列。

公开(公告)号：US08266596B2

公开(公告)日：2012-09-11

申请号：US12713817

申请日：2010-02-26

申请人： Yuji Ishikawa ,  Yutaka Ota ,  Yu Nakanishi

发明人： Yuji Ishikawa ,  Yutaka Ota ,  Yu Nakanishi

IPC分类号： G06F9/44

CPC分类号： G06F8/51

摘要： Every time an assignment statement is executed during performing a simulation according to a second variable memory system, it is determined whether a value interpreted to have the same meaning is assigned to the assignment statement in the simulation according to a first variable memory system and in the simulation according to the second variable memory system. When the value interpreted to have the same meaning is not assigned, the value assigned according to the second variable memory system is overwritten by an expected value, and a report indicating that the assignment statement is a part dependent on a variable memory system is output.

摘要翻译： 在根据第二可变存储器系统执行仿真期间每次执行分配语句时，根据第一可变存储器系统确定在模拟中是否将解释为具有相同含义的值分配给模拟中的赋值语句，并且在 根据第二个可变存储器系统进行仿真。 当被解释为具有相同含义的值被分配时，根据第二变量存储器系统分配的值被预期值覆盖，并且输出指示分配语句是依赖于可变存储器系统的部分的报告。