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    Variable resistance memory
    4.
    发明授权
    Variable resistance memory 有权

    公开(公告)号：US09905611B2

    公开(公告)日：2018-02-27

    申请号：US15065506

    申请日：2016-03-09

    申请人： TOSHIBA MEMORY CORPORATION

    发明人： Yoshihiro Ueda

    IPC分类号： H01L27/00 ,  H01L27/22 ,  H01L23/528 ,  G11C11/16 ,  H01L27/24

    CPC分类号： H01L27/228 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1659 ,  H01L23/528 ,  H01L27/101 ,  H01L27/2454

    摘要： According to one embodiment, a variable resistance memory includes first and second semiconductor regions in a layer; a memory cell on the first semiconductor region, the memory cell including a first transistor having a first gate connected to a word line and a memory element, the word line extending in a first direction parallel to a surface of the layer; and a second transistor on the second semiconductor region and connected to the memory cell via a bit line, the bit line extending a second direction parallel to the surface of the layer, and the second direction intersecting the first direction. The second semiconductor region extends in a third direction parallel to the surface of the substrate and the third direction intersects the first and second directions.

    Array Of Memory Cells And Methods Of Forming An Array Of Memory Cells
    6.
    发明申请
    Array Of Memory Cells And Methods Of Forming An Array Of Memory Cells 有权

    公开(公告)号：US20170338280A1

    公开(公告)日：2017-11-23

    申请号：US15159984

    申请日：2016-05-20

    申请人： Micron Technology, Inc.

    发明人： Denzil S. Frost ,  Tuman Earl Allen, III

    IPC分类号： H01L27/24 ,  H01L23/528 ,  H01L45/00 ,  H01L27/10

    CPC分类号： H01L27/2463 ,  H01L23/528 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/1608 ,  H01L45/1675

    摘要： A method of forming an array of memory cells comprises forming an elevationally inner tier of memory cells comprising spaced inner tier lower first conductive lines, spaced inner tier upper second conductive lines, and programmable material of individual inner tier memory cells elevationally between the inner tier first lines and the inner tier second lines where such cross. First insulative material is formed laterally between the inner tier second lines to have respective elevationally outermost surfaces that are lower than elevationally outermost surfaces of immediately laterally-adjacent of the inner tier second lines. Second insulative material is formed elevationally over the first insulative material and laterally between the inner tier second lines. The second insulative material is of different composition from that of the first insulative material. An elevationally outer tier of memory cells is formed to comprise spaced outer tier lower first conductive lines, spaced outer tier upper second conductive lines, and programmable material of individual outer tier memory cells elevationally between the outer tier first lines and the outer tier second lines where such cross. Arrays of memory cells independent of method of manufacture are disclosed.