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30 条记录 (耗时 0.024 秒)

    Data buffer circuit, interface circuit and control method therefor
    1.
    发明授权
    Data buffer circuit, interface circuit and control method therefor 有权
    数据缓冲电路，接口电路及其控制方法

    公开(公告)号：US07454589B2

    公开(公告)日：2008-11-18

    申请号：US11102656

    申请日：2005-04-11

    申请人： Kazuya Taniguchi ,  Toshiyuki Nishii ,  Hiromichi Mizuno ,  Tsutomu Terazawa

    发明人： Kazuya Taniguchi ,  Toshiyuki Nishii ,  Hiromichi Mizuno ,  Tsutomu Terazawa

    IPC分类号： G06F1/12

    CPC分类号： G06F13/405

    摘要： There are provided a buffer circuit buffers data between a synchronous circuit and an asynchronous circuit, and a control method therefor. There are also provided an interface circuit that controls data transfer between a synchronous memory circuit and the asynchronous circuit, and a control method therefor, which are used in the buffer circuit and the control method therefor. A data buffer circuit that is interposed between an image processing system and a main system includes a one-port RAM, a control signal generating section, an subsequent cycle address generating section, and a first selector. The first selector selectively outputs the present cycle address to an address of the one-port RAM when an access to the one-port RAM is a write access, and selectively outputs the subsequent cycle address to the address of the one-port RAM when the access to the one-port RAM is a read access.

    摘要翻译： 提供缓冲电路缓冲同步电路和异步电路之间的数据及其控制方法。 还提供了一种控制同步存储器电路和异步电路之间的数据传输的接口电路及其控制方法，其用于缓冲电路及其控制方法。 介于图像处理系统和主系统之间的数据缓冲电路包括单端口RAM，控制信号产生部分，后续周期地址生成部分和第一选择器。 当对单端口RAM的访问是写访问时，第一选择器有选择地将当前周期地址输出到单端口RAM的地址，并且当第一选择器输入后续周期地址到单端口RAM的地址时 访问单端口RAM是一种读取访问。

    Data buffer circuit, interface circuit and control method therefor
    2.
    发明申请
    Data buffer circuit, interface circuit and control method therefor 有权
    数据缓冲电路，接口电路及其控制方法

    公开(公告)号：US20060129720A1

    公开(公告)日：2006-06-15

    申请号：US11102656

    申请日：2005-04-11

    申请人： Kazuya Taniguchi ,  Toshiyuki Nishii ,  Hiromichi Mizuno ,  Tsutomu Terazawa

    发明人： Kazuya Taniguchi ,  Toshiyuki Nishii ,  Hiromichi Mizuno ,  Tsutomu Terazawa

    IPC分类号： G06F3/06

    CPC分类号： G06F13/405

    摘要： There are provided a buffer circuit buffers data between a synchronous circuit and an asynchronous circuit, and a control method therefor. There are also provided an interface circuit that controls data transfer between a synchronous memory circuit and the asynchronous circuit, and a control method therefor, which are used in the buffer circuit and the control method therefor. A data buffer circuit that is interposed between an image processing system and a main system includes a one-port RAM, a control signal generating section, an subsequent cycle address generating section, and a first selector. The first selector selectively outputs the present cycle address to an address of the one-port RAM when an access to the one-port RAM is a write access, and selectively outputs the subsequent cycle address to the address of the one-port RAM when the access to the one-port RAM is a read access.

    摘要翻译： 提供缓冲电路缓冲同步电路和异步电路之间的数据及其控制方法。 还提供了一种控制同步存储器电路和异步电路之间的数据传送的接口电路及其控制方法，其用于缓冲电路及其控制方法。 介于图像处理系统和主系统之间的数据缓冲电路包括单端口RAM，控制信号产生部分，后续周期地址生成部分和第一选择器。 当对单端口RAM的访问是写访问时，第一选择器有选择地将当前周期地址输出到单端口RAM的地址，并且当第一选择器输入后续周期地址到单端口RAM的地址时 访问单端口RAM是一种读取访问。

    Semiconductor device including voltage level conversion output circuit
    3.
    发明申请
    Semiconductor device including voltage level conversion output circuit 有权
    半导体器件包括电压电平转换输出电路

    公开(公告)号：US20070109901A1

    公开(公告)日：2007-05-17

    申请号：US11652589

    申请日：2007-01-12

    申请人： Kazuya Taniguchi ,  Toshiyuki Nishii ,  Hiromichi Mizuno

    发明人： Kazuya Taniguchi ,  Toshiyuki Nishii ,  Hiromichi Mizuno

    IPC分类号： G11C5/14

    CPC分类号： G11C5/025 ,  G11C5/14 ,  G11C5/143 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084

    摘要： A semiconductor device for easily changing an operating voltage of an I/O circuit. The I/O circuit includes a first I/O cell, which operates with a first high-potential power supply, and a second I/O cell, which operates with a second high-potential power supply. The I/O circuit includes a control circuit for selectively activating the first and second I/O cells according to a voltage selection signal. In the I/O circuit, a signal having a voltage according to an operating voltage of the selected I/O cell is generated.

    摘要翻译： 一种用于容易地改变I / O电路的工作电压的半导体器件。 I / O电路包括用第一高电位电源操作的第一I / O单元和与第二高电位电源一起工作的第二I / O单元。 I / O电路包括用于根据电压选择信号选择性地激活第一和第二I / O单元的控制电路。 在I / O电路中，产生具有根据所选I / O单元的工作电压的电压的信号。

    Semiconductor device including voltage level conversion output circuit
    4.
    发明授权
    Semiconductor device including voltage level conversion output circuit 有权
    半导体器件包括电压电平转换输出电路

    公开(公告)号：US07408831B2

    公开(公告)日：2008-08-05

    申请号：US11652590

    申请日：2007-01-12

    申请人： Kazuya Taniguchi ,  Toshiyuki Nishii ,  Hiromichi Mizuno

    发明人： Kazuya Taniguchi ,  Toshiyuki Nishii ,  Hiromichi Mizuno

    IPC分类号： G11C5/14

    CPC分类号： G11C5/025 ,  G11C5/14 ,  G11C5/143 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084

    摘要： A semiconductor device for easily changing an operating voltage of an I/O circuit. The I/O circuit includes a first I/O cell, which operates with a first high-potential power supply, and a second I/O cell, which operates with a second high-potential power supply. The I/O circuit includes a control circuit for selectively activating the first and second I/O cells according to a voltage selection signal. In the I/O circuit, a signal having a voltage according to an operating voltage of the selected I/O cell is generated.

    摘要翻译： 一种用于容易地改变I / O电路的工作电压的半导体器件。 I / O电路包括用第一高电位电源操作的第一I / O单元和与第二高电位电源一起工作的第二I / O单元。 I / O电路包括用于根据电压选择信号选择性地激活第一和第二I / O单元的控制电路。 在I / O电路中，产生具有根据所选I / O单元的工作电压的电压的信号。

    Semiconductor device including voltage level conversion output circuit
    5.
    发明授权
    Semiconductor device including voltage level conversion output circuit 有权
    半导体器件包括电压电平转换输出电路

    公开(公告)号：US07512031B2

    公开(公告)日：2009-03-31

    申请号：US11652591

    申请日：2007-01-12

    申请人： Kazuya Taniguchi ,  Toshiyuki Nishii ,  Hiromichi Mizuno

    发明人： Kazuya Taniguchi ,  Toshiyuki Nishii ,  Hiromichi Mizuno

    IPC分类号： G11C5/14

    CPC分类号： G11C5/025 ,  G11C5/14 ,  G11C5/143 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084

    摘要： A semiconductor device for easily changing an operating voltage of an I/O circuit. The I/O circuit includes a first I/O cell, which operates with a first high-potential power supply, and a second I/O cell, which operates with a second high-potential power supply. The I/O circuit includes a control circuit for selectively activating the first and second I/O cells according to a voltage selection signal. In the I/O circuit, a signal having a voltage according to an operating voltage of the selected I/O cell is generated.

    摘要翻译： 一种用于容易地改变I / O电路的工作电压的半导体器件。 I / O电路包括用第一高电位电源操作的第一I / O单元和与第二高电位电源一起工作的第二I / O单元。 I / O电路包括用于根据电压选择信号选择性地激活第一和第二I / O单元的控制电路。 在I / O电路中，产生具有根据所选I / O单元的工作电压的电压的信号。