公开(公告)号：US07454589B2

公开(公告)日：2008-11-18

申请号：US11102656

申请日：2005-04-11

申请人： Kazuya Taniguchi ,  Toshiyuki Nishii ,  Hiromichi Mizuno ,  Tsutomu Terazawa

发明人： Kazuya Taniguchi ,  Toshiyuki Nishii ,  Hiromichi Mizuno ,  Tsutomu Terazawa

IPC分类号： G06F1/12

CPC分类号： G06F13/405

摘要： There are provided a buffer circuit buffers data between a synchronous circuit and an asynchronous circuit, and a control method therefor. There are also provided an interface circuit that controls data transfer between a synchronous memory circuit and the asynchronous circuit, and a control method therefor, which are used in the buffer circuit and the control method therefor. A data buffer circuit that is interposed between an image processing system and a main system includes a one-port RAM, a control signal generating section, an subsequent cycle address generating section, and a first selector. The first selector selectively outputs the present cycle address to an address of the one-port RAM when an access to the one-port RAM is a write access, and selectively outputs the subsequent cycle address to the address of the one-port RAM when the access to the one-port RAM is a read access.

摘要翻译： 提供缓冲电路缓冲同步电路和异步电路之间的数据及其控制方法。 还提供了一种控制同步存储器电路和异步电路之间的数据传输的接口电路及其控制方法，其用于缓冲电路及其控制方法。 介于图像处理系统和主系统之间的数据缓冲电路包括单端口RAM，控制信号产生部分，后续周期地址生成部分和第一选择器。 当对单端口RAM的访问是写访问时，第一选择器有选择地将当前周期地址输出到单端口RAM的地址，并且当第一选择器输入后续周期地址到单端口RAM的地址时 访问单端口RAM是一种读取访问。

公开(公告)号：US20060129720A1

公开(公告)日：2006-06-15

申请号：US11102656

申请日：2005-04-11

申请人： Kazuya Taniguchi ,  Toshiyuki Nishii ,  Hiromichi Mizuno ,  Tsutomu Terazawa

发明人： Kazuya Taniguchi ,  Toshiyuki Nishii ,  Hiromichi Mizuno ,  Tsutomu Terazawa

IPC分类号： G06F3/06

CPC分类号： G06F13/405

摘要： There are provided a buffer circuit buffers data between a synchronous circuit and an asynchronous circuit, and a control method therefor. There are also provided an interface circuit that controls data transfer between a synchronous memory circuit and the asynchronous circuit, and a control method therefor, which are used in the buffer circuit and the control method therefor. A data buffer circuit that is interposed between an image processing system and a main system includes a one-port RAM, a control signal generating section, an subsequent cycle address generating section, and a first selector. The first selector selectively outputs the present cycle address to an address of the one-port RAM when an access to the one-port RAM is a write access, and selectively outputs the subsequent cycle address to the address of the one-port RAM when the access to the one-port RAM is a read access.

摘要翻译： 提供缓冲电路缓冲同步电路和异步电路之间的数据及其控制方法。 还提供了一种控制同步存储器电路和异步电路之间的数据传送的接口电路及其控制方法，其用于缓冲电路及其控制方法。 介于图像处理系统和主系统之间的数据缓冲电路包括单端口RAM，控制信号产生部分，后续周期地址生成部分和第一选择器。 当对单端口RAM的访问是写访问时，第一选择器有选择地将当前周期地址输出到单端口RAM的地址，并且当第一选择器输入后续周期地址到单端口RAM的地址时 访问单端口RAM是一种读取访问。