-
公开(公告)号：US08050066B2
公开(公告)日：2011-11-01
申请号：US12101959
申请日：2008-04-11
IPC分类号： H02M7/48 , H01L27/108
CPC分类号： H01L27/0805 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： The present invention aims to enhance the reliability of a semiconductor device having first through fourth capacitive elements. The first through fourth capacitive elements are disposed over a semiconductor substrate. A series circuit of the first and second capacitive elements and a series circuit of the third and fourth capacitive elements are coupled in parallel between first and second potentials. Lower electrodes of the first and third capacitive elements are respectively formed by a common conductor pattern and coupled to the first potential. Lower electrodes of the second and fourth capacitive elements are respectively formed by a conductor pattern of the same layer as the above conductor pattern and coupled to the second potential. Upper electrodes of the first and second capacitive elements are respectively formed by a common conductor pattern and brought to a floating potential. Upper electrodes of the third and fourth capacitive elements are respectively formed by a conductor pattern of the same layer as the above conductor pattern and brought to a floating potential, but not coupled to the upper electrodes of the first and second capacitive elements by a conductor.
摘要翻译： 本发明旨在提高具有第一至第四电容元件的半导体器件的可靠性。 第一至第四电容元件设置在半导体衬底上。 第一和第二电容元件的串联电路和第三和第四电容元件的串联电路在第一和第二电位之间并联耦合。 第一和第三电容元件的下电极分别由公共导体图案形成并耦合到第一电位。 第二和第四电容元件的下电极分别由与上述导体图案相同的层的导体图案形成并耦合到第二电位。 第一和第二电容元件的上电极分别由公共导体图形形成并且具有浮动电位。 第三和第四电容元件的上电极分别由与上述导体图案相同的层的导体图形形成浮动电位，但不通过导体耦合到第一和第二电容元件的上电极。
-
公开(公告)号：US20080283889A1
公开(公告)日：2008-11-20
申请号：US12101959
申请日：2008-04-11
CPC分类号： H01L27/0805 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： The present invention aims to enhance the reliability of a semiconductor device having first through fourth capacitive elements. The first through fourth capacitive elements are disposed over a semiconductor substrate. A series circuit of the first and second capacitive elements and a series circuit of the third and fourth capacitive elements are coupled in parallel between first and second potentials. Lower electrodes of the first and third capacitive elements are respectively formed by a common conductor pattern and coupled to the first potential. Lower electrodes of the second and fourth capacitive elements are respectively formed by a conductor pattern of the same layer as the above conductor pattern and coupled to the second potential. Upper electrodes of the first and second capacitive elements are respectively formed by a common conductor pattern and brought to a floating potential. Upper electrodes of the third and fourth capacitive elements are respectively formed by a conductor pattern of the same layer as the above conductor pattern and brought to a floating potential, but not coupled to the upper electrodes of the first and second capacitive elements by a conductor.
摘要翻译： 本发明旨在提高具有第一至第四电容元件的半导体器件的可靠性。 第一至第四电容元件设置在半导体衬底上。 第一和第二电容元件的串联电路和第三和第四电容元件的串联电路在第一和第二电位之间并联耦合。 第一和第三电容元件的下电极分别由公共导体图案形成并耦合到第一电位。 第二和第四电容元件的下电极分别由与上述导体图案相同的层的导体图案形成并耦合到第二电位。 第一和第二电容元件的上电极分别由公共导体图形形成并且具有浮动电位。 第三和第四电容元件的上电极分别由与上述导体图案相同的层的导体图形形成浮动电位，但不通过导体耦合到第一和第二电容元件的上电极。
-
搜索结果
2 条记录 (耗时 0.02 秒)
