公开(公告)号：US20070035500A1

公开(公告)日：2007-02-15

申请号：US11161646

申请日：2005-08-11

申请人： Keisuke Takeo ,  Yasuhiro Gen ,  Masahiro Kaneko ,  Hitoshi Oikawa

发明人： Keisuke Takeo ,  Yasuhiro Gen ,  Masahiro Kaneko ,  Hitoshi Oikawa

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G2300/0426 ,  G09G2330/021

摘要： A data bus structure, a driver therewith, and a display with a driver capable of low power consumption are provided herewith. In the proposed structure, data lines of the data bus corresponding to a plurality of output channels are divided by alternatively inserting isolating elements. By controlling these isolating elements, current will be alternatively isolated from a portion of the bus and power consumption is significantly reduced. In the proposed structure, different function and settings can be determined in advance in consideration of where data is taken into the bus line.

摘要翻译： 本文提供了一种数据总线结构，其驱动器以及具有能够实现低功耗的驱动器的显示器。 在所提出的结构中，对应于多个输出通道的数据总线的数据线通过交替地插入隔离元件来划分。 通过控制这些隔离元件，电流将与总线的一部分备​​选地隔离，并且功耗显着降低。 在所提出的结构中，考虑到数据在总线上的位置，可以预先确定不同的功能和设置。

公开(公告)号：US06967883B2

公开(公告)日：2005-11-22

申请号：US10624814

申请日：2003-07-22

申请人： Masayuki Hira ,  Takahiro Matsuzawa ,  Yoritaka Saitoh ,  Keisuke Takeo

发明人： Masayuki Hira ,  Takahiro Matsuzawa ,  Yoritaka Saitoh ,  Keisuke Takeo

IPC分类号： G11C11/419 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C11/41 ,  G11C7/00

CPC分类号： G11C7/06 ,  G11C7/1006 ,  G11C7/12 ,  G11C2207/005 ,  G11C2207/065 ,  G11C2207/104

摘要： This invention provides a type of sense amplifier, a type of bit line circuit, a type of storage device, and a method for amplifying a read signal characterized by the fact that it has a small detection error of the read signal and has low power consumption. With bit lines (BL, BLZ) and input terminals (SA, SAZ) of the amplifier connected to each other by means of a CMOS switch circuit, as control signal ENN becomes high level, amplification of the read signal in the amplifier starts and, at the same time, the amplified signal is held. After a time delay determined by delay circuit U1 from the start of amplification of the read signal, control signal GEN1 and control signal GEN2 output from said delay circuit U1 are changed, and connection between the bit line and amplifier is cut off. Consequently, while the small potential difference at the start of amplification is kept by the current from the bit line, the amplification operation is carried out to a certain degree, and then the bit line is cut off from the amplifier. Consequently, a detection error in the read signal can hardly take place.

摘要翻译： 本发明提供一种读出放大器，一种位线电路，一种存储装置和一种用于放大读取信号的方法，其特征在于它具有读取信号的较小检测误差并具有低功耗 。 利用CMOS开关电路将放大器的位线（BL，BLZ）和输入端子（SA，SAZ）彼此连接，随着控制信号ENN变为高电平，放大器中的读取信号的放大开始， 同时保持放大的信号。 在延迟电路U 1从读取信号的放大开始确定的时间延迟之后，从所述延迟电路U 1输出的控制信号GEN 1和控制信号GEN 2被改变，并且位线和放大器之间的连接被切断 。 因此，当通过来自位线的电流保持放大开始时的小电位差时，在一定程度上进行放大操作，然后从放大器切断位线。 因此，难以发生读取信号的检测误差。