公开(公告)号：US20190206482A1

公开(公告)日：2019-07-04

申请号：US16294655

申请日：2019-03-06

Applicant: SK hynix Inc.

Inventor： Hyung Sik WON ,  Jae Jin LEE

IPC: G11C11/4094 ,  G11C11/4074 ,  G11C11/4091 ,  G11C11/4097 ,  G11C7/08

CPC classification number: G11C11/4094 ,  G11C5/147 ,  G11C7/08 ,  G11C11/404 ,  G11C11/4074 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

Abstract: A semiconductor device is disclosed, which relates to a technology for a sense-amplifier (sense-amp) configured to compensate for mismatch of a sensing bit-line. The semiconductor device includes a sense-amplifier configured to selectively control connection between a pair of bit lines and a pair of sensing bit lines in response to a connection control signal in an offset compensation period, and precharge a pull-down power-supply line with a bit line precharge voltage level in the offset compensation period. The semiconductor device also includes a pull-down voltage controller configured to increase a voltage of the pull-down power-supply line by a predetermined level in response to a pull-down control signal in the offset compensation period.

公开(公告)号：US20190122721A1

公开(公告)日：2019-04-25

申请号：US16227771

申请日：2018-12-20

Applicant: Apple Inc.

Inventor： Edward M. McCombs

IPC: G11C11/4096 ,  G06F12/0875 ,  G11C11/408 ,  G11C11/4091

CPC classification number: G11C11/4096 ,  G06F12/0862 ,  G06F12/0875 ,  G06F2212/1028 ,  G06F2212/452 ,  G06F2212/6028 ,  G11C5/145 ,  G11C7/1096 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/419 ,  G11C2207/005

Abstract: Techniques for implementing a storage array write driver with a reduced-power boost circuit. An apparatus may include a bit cell configured to store data, a bit line circuit coupled to convey data to the bit cell, a write driver circuit configured to transmit write data to the bit cell via the bit line circuit, and a boost circuit that is distinct from the write driver circuit. The boost circuit may be selectively coupled to drive the bit line circuit below a ground voltage dependent on activation of a boost signal and the write data being in a logic low state. The boost circuit may also be coupled to the bit line circuit at a location that is closer to the bit cell than to the write driver circuit, and may be sized to discharge the bit line circuit without being sized to discharge internal capacitance of the write driver.

公开(公告)号：US20180366165A1

公开(公告)日：2018-12-20

申请号：US16111085

申请日：2018-08-23

Applicant: Micron Technology, Inc.

Inventor： Glen E. Hush

IPC: G11C7/06 ,  G11C11/4091 ,  G11C7/10 ,  G11C7/12 ,  G11C11/4094

CPC classification number: G11C7/065 ,  G11C7/1006 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/005

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry can include a sense amplifier coupled to a pair of complementary sense lines and a compute component coupled to the sense amplifier via pass gates coupled to logical operation selection logic. The logical operation selection logic can be configured to control pass gates based on a selected logical operation.

公开(公告)号：US20180233192A1

公开(公告)日：2018-08-16

申请号：US15701754

申请日：2017-09-12

Applicant: SK hynix Inc.

Inventor： Hyung Sik WON ,  Jae Jin LEE

IPC: G11C11/4094 ,  G11C11/404 ,  G11C11/4074

CPC classification number: G11C11/4094 ,  G11C7/08 ,  G11C11/404 ,  G11C11/4074 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

Abstract: A semiconductor device is disclosed, which relates to a technology for a sense-amplifier (sense-amp) configured to compensate for mismatch of a sensing bit-line. The semiconductor device includes a sense-amplifier configured to selectively control connection between a pair of bit lines and a pair of sensing bit lines in response to a connection control signal in an offset compensation period, and precharge a pull-down power-supply line with a bit line precharge voltage level in the offset compensation period. The semiconductor device also includes a pull-down voltage controller configured to increase a voltage of the pull-down power-supply line by a predetermined level in response to a pull-down control signal in the offset compensation period.

公开(公告)号：US20180197601A1

公开(公告)日：2018-07-12

申请号：US15911824

申请日：2018-03-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mahmut Sinangil ,  Hidehiro Fujiwara ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang ,  Yen-Huei Chen ,  Sahil Preet Singh

IPC: G11C11/419 ,  G11C11/412 ,  G11C8/16 ,  G11C7/16 ,  G11C7/18 ,  G11C8/12

CPC classification number: G11C11/419 ,  G11C7/16 ,  G11C7/18 ,  G11C8/12 ,  G11C8/16 ,  G11C11/412 ,  G11C2207/005

Abstract: In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.

公开(公告)号：US10002666B2

公开(公告)日：2018-06-19

申请号：US15664546

申请日：2017-07-31

Applicant: Micron Technology, Inc.

Inventor： Kazuhiko Kajigaya

IPC: G11C5/06 ,  G11C14/00 ,  G11C11/4096 ,  G11C11/4093 ,  G11C11/4091 ,  G11C11/22 ,  G11C7/10 ,  G11C7/22

CPC classification number: G11C14/0027 ,  G06F12/02 ,  G06F12/0215 ,  G06F2212/1016 ,  G06F2212/1036 ,  G06F2212/1041 ,  G06F2212/205 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1015 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/14 ,  G11C7/22 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/005

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. One method includes determining whether to access a first memory cell of a first memory cell array or a second memory cell of a second memory cell array, where a first digit line coupled to the first memory cell is coupled to a paging buffer register including a sense amplifier. The method further includes operating a transfer gate based at least in part on determining to read the second memory cell of the second memory cell array, where the transfer gate is configured to selectively couple a second digit line coupled to the second memory cell to the paging buffer register through the first digit line.

公开(公告)号：US09966120B2

公开(公告)日：2018-05-08

申请号：US15391392

申请日：2016-12-27

Applicant: SK hynix Inc.

Inventor： One Gyun Na

IPC: G11C11/4091 ,  G11C7/22 ,  G11C7/12

CPC classification number: G11C7/22 ,  G11C7/065 ,  G11C7/08 ,  G11C7/1048 ,  G11C7/12 ,  G11C7/18 ,  G11C2207/002 ,  G11C2207/005

Abstract: A data sensing circuit may include a pair of first signal lines, and a pair of second signal lines precharged with a first power supply voltage. The data sensing circuit may also include a line level control block configured for applying a second power supply voltage to any one signal line of the pair of second signal lines in response to a read command.

公开(公告)号：US20180114551A1

公开(公告)日：2018-04-26

申请号：US15797759

申请日：2017-10-30

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Harish N. Venkata

IPC: G11C7/06 ,  H03K19/20

CPC classification number: G11C7/06 ,  G11C7/065 ,  G11C7/08 ,  G11C7/1006 ,  G11C8/12 ,  G11C11/4091 ,  G11C2207/002 ,  G11C2207/005 ,  H03K19/20

Abstract: The present disclosure includes apparatuses and methods related to selectively performing logical operations. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component. A controller is coupled to sensing circuitry and is configured to cause storing of an indication of whether a logical operation is to be selectively performed between an operand stored in the sensing circuitry and an operand stored in the sense amplifier.

公开(公告)号：US09922700B2

公开(公告)日：2018-03-20

申请号：US15162711

申请日：2016-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mahmut Sinangil ,  Hidehiro Fujiwara ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang ,  Yen-Huei Chen ,  Sahil Preet Singh

IPC: G11C11/00 ,  G11C11/419 ,  G11C8/12 ,  G11C11/412 ,  G11C7/16 ,  G11C8/16 ,  G11C7/18

CPC classification number: G11C11/419 ,  G11C7/16 ,  G11C7/18 ,  G11C8/12 ,  G11C8/16 ,  G11C11/412 ,  G11C2207/005

Abstract: In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.

公开(公告)号：US09905278B2

公开(公告)日：2018-02-27

申请号：US14859884

申请日：2015-09-21

Applicant: Intel Corporation

Inventor： Jaydeep Kulkarni

IPC: G11C7/12 ,  G11C8/08 ,  G11C8/10

CPC classification number: G11C7/12 ,  G11C7/1048 ,  G11C8/08 ,  G11C8/10 ,  G11C17/12 ,  G11C2207/005

Abstract: Some embodiments include apparatuses and methods having non-volatile memory cells, a data line associated with a group of non-volatile memory cells of the non-volatile memory cells, a first transistor coupled to the data line and a node, a second transistor coupled to the node and an additional node, a pull-up component coupled to the node and a supply node, and an additional pull-up component coupled to the additional node and the supply node.