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1.发明授权Method, apparatus and program product for automatic placement and routing of integrated circuit 失效用于集成电路自动放置和布线的方法，设备和程序产品公开(公告)号：US06968521B2
公开(公告)日：2005-11-22
申请号：US10331513
申请日：2002-12-31
CPC分类号： G06F17/5072
摘要： After automatic cell placement, the following steps are performed before performing automatic inter-cell routing. (S22) Estimated wires having Manhattan-length path are connected between same-node terminals of cells, and detected and counted is a crosstalk error that parallel-wire length is more than a predetermined value. (S23) The detected error is resolved by moving cells closely spaced less than a predetermined interval apart and connected to the error-detected estimated wires; the cell movement data is stored in a storage device; and such processes are repeated N times; and the cell placement data is modified on the basis of the cell movement data corresponding to the minimum value of error-count values of all the N times. (S24) If the minimum value is not 0, (S25) a buffer cell is inserted in the error-detected estimated wire. (S27) Obtained is the wire density of estimated wiring having Manhattan-length path, and if the density is more than a predetermined value, the design-target frame is enlarged in size, and the process returns to the automatic cell placement process.
摘要翻译： 在自动单元格放置之后，在执行自动单元间路由之前执行以下步骤。 （S22）具有曼哈顿长度路径的估计线路连接在小区的相同节点终端之间，并且被检测和计数是并行线长度大于预定值的串扰误差。 （S23）检测到的误差通过移动细胞间隔小于预定间隔的距离并连接到检错估计的线来解决; 单元移动数据存储在存储装置中; 并且这样的处理重复N次; 并且基于与所有N次的误差计数值的最小值相对应的单元移动数据来修改单元布置数据。 （S24）如果最小值不为0，则将（S25）缓冲单元插入到检测出的误差线中。 （S27）获得具有曼哈顿路径的估计布线的线密度，并且如果密度大于预定值，则设计目标帧的尺寸被放大，并且处理返回到自动单元放置处理。
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2.发明授权Apparatus and method for design support using layout positions of first and second terminals 有权使用第一和第二终端的布局位置的设计支持的装置和方法公开(公告)号：US08584069B2
公开(公告)日：2013-11-12
申请号：US12892481
申请日：2010-09-28
申请人： Kenichi Ushiyama , Shigenori Ichinose , Kenji Suzuki , Kenji Kumagai , Takafumi Miyahara , Shuji Tanahashi , Hideto Fukuda
发明人： Kenichi Ushiyama , Shigenori Ichinose , Kenji Suzuki , Kenji Kumagai , Takafumi Miyahara , Shuji Tanahashi , Hideto Fukuda
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A design support method executed by a computer includes: detecting a layout position of a first terminal in a cell as a first layout position from layout data including a cell of a macro which is arranged at a plurality of orientations, the first terminal being arranged at a first orientation; calculating a second layout position of a first terminal which is arranged at a second orientation which is different from the first orientation based on a variation from the first orientation to the second orientation and the first layout position; associating the second layout position with the first layout position and the layout data; and outputting an association result.
摘要翻译： 由计算机执行的设计支持方法包括：从包括布置在多个方向上的宏单元的布局数据中检测单元中的第一终端的布局位置作为第一布局位置，所述第一终端布置在 第一个方向; 基于从所述第一取向到所述第二取向和所述第一布局位置的变化，计算布置在与所述第一取向不同的第二取向的第一端子的第二布局位置; 将第二布局位置与第一布局位置和布局数据相关联; 并输出关联结果。
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公开(公告)号：US20050006781A1
公开(公告)日：2005-01-13
申请号：US10914163
申请日：2004-08-10
IPC分类号： G06F17/50 , H01L21/82 , H01L21/822 , H01L23/522 , H01L27/04 , H01L23/48
CPC分类号： H01L23/5225 , G06F17/5077 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit includes a shielded wire line and a shielding wire line provided for the shielded wire line and divided into a plurality of segments in a longitudinal direction of the shielded wire line.
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公开(公告)号：US20110078646A1
公开(公告)日：2011-03-31
申请号：US12892481
申请日：2010-09-28
申请人： Kenichi Ushiyama , Shigenori Ichinose , Kenji Suzuki , Kenji Kumagai , Takafumi Miyahara , Shuji Tanahashi , Hideto Fukuda
发明人： Kenichi Ushiyama , Shigenori Ichinose , Kenji Suzuki , Kenji Kumagai , Takafumi Miyahara , Shuji Tanahashi , Hideto Fukuda
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A design support method executed by a computer includes: detecting a layout position of a first terminal in a cell as a first layout position from layout data including a cell of a macro which is arranged at a plurality of orientations, the first terminal being arranged at a first orientation; calculating a second layout position of a first terminal which is arranged at a second orientation which is different from the first orientation based on a variation from the first orientation to the second orientation and the first layout position; associating the second layout position with the first layout position and the layout data; and outputting an association result.
摘要翻译： 由计算机执行的设计支持方法包括：从包括布置在多个方向上的宏单元的布局数据中检测单元中的第一终端的布局位置作为第一布局位置，所述第一终端布置在 第一个方向; 基于从所述第一取向到所述第二取向和所述第一布局位置的变化，计算布置在与所述第一取向不同的第二取向的第一端子的第二布局位置; 将第二布局位置与第一布局位置和布局数据相关联; 并输出关联结果。
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公开(公告)号：US07339250B2
公开(公告)日：2008-03-04
申请号：US10914163
申请日：2004-08-10
IPC分类号： H01L29/00 , H01L23/552
CPC分类号： H01L23/5225 , G06F17/5077 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit includes a shielded wire line and a shielding wire line provided for the shielded wire line and divided into a plurality of segments in a longitudinal direction of the shielded wire line.
摘要翻译： 半导体集成电路包括屏蔽线和屏蔽线线设置的屏蔽线，并且在屏蔽线的纵向上分为多个段。
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6.发明授权Method for determining a length of shielding of a semiconductor integrated circuit wiring 有权用于确定半导体集成电路布线的屏蔽长度的方法公开(公告)号：US07913212B2
公开(公告)日：2011-03-22
申请号：US12071845
申请日：2008-02-27
CPC分类号： H01L23/5225 , G06F17/5077 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit includes a shielded wire line and a shielding wire line provided for the shielded wire line and divided into a plurality of segments in a longitudinal direction of the shielded wire line.
摘要翻译： 半导体集成电路包括屏蔽线和屏蔽线线设置的屏蔽线，并且在屏蔽线的纵向上分为多个段。
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公开(公告)号：US20080301610A1
公开(公告)日：2008-12-04
申请号：US12071845
申请日：2008-02-27
IPC分类号： G06F17/50
CPC分类号： H01L23/5225 , G06F17/5077 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit includes a shielded wire line and a shielding wire line provided for the shielded wire line and divided into a plurality of segments in a longitudinal direction of the shielded wire line.
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公开(公告)号：US06972493B2
公开(公告)日：2005-12-06
申请号：US10694997
申请日：2003-10-29
IPC分类号： G06F17/50 , H01L21/82 , H01L21/822 , H01L23/522 , H01L27/04 , H01L29/40
CPC分类号： H01L23/5225 , G06F17/5077 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit includes a shielded wire line and a shielding wire line provided for the shielded wire line and divided into a plurality of segments in a longitudinal direction of the shielded wire line.
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公开(公告)号：US06664638B2
公开(公告)日：2003-12-16
申请号：US09963469
申请日：2001-09-27
IPC分类号： H01L2348
CPC分类号： H01L23/5225 , G06F17/5077 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit includes a shielded wire line and a shielding wire line provided for the shielded wire line and divided into a plurality of segments in a longitudinal direction of the shielded wire line.
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公开(公告)号：US07361975B2
公开(公告)日：2008-04-22
申请号：US10914141
申请日：2004-08-10
IPC分类号： H01L39/00
CPC分类号： H01L23/5225 , G06F17/5077 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit, includes a shielded wire line and a shielding wire line provided for the shielded wire line and divided into a plurality of segments in a longitudinal direction of the shielded wire line.
摘要翻译： 一种半导体集成电路，包括屏蔽线和屏蔽线线，屏蔽线线沿屏蔽线线的纵向方向分成多个段。
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