Semiconductor device manufactured by the damascene process having improved stress migration resistance
    1.
    发明授权
    Semiconductor device manufactured by the damascene process having improved stress migration resistance 有权
    通过镶嵌工艺制造的具有改善的耐应力迁移性的半导体器件

    公开(公告)号:US07173337B2

    公开(公告)日:2007-02-06

    申请号:US11035745

    申请日:2005-01-18

    IPC分类号: H01L23/48

    摘要: A semiconductor device including a second insulating film formed on a substantially flat surface, on which a surface of a first wiring and a surface of a first insulating film are continued, to cover the first wiring, a wiring trench formed in the second insulating film, connection holes formed in the second insulating film to extend from the wiring trench to the first wiring, dummy connection holes formed in the second insulating film to extend from the wiring trench to a non-forming region of the first wiring, and a second wiring buried in the connection holes and the wiring trench to be connected electrically to the first wiring and also buried in the dummy connection holes, and formed such that a surface of the second wiring and a surface of the second insulating film constitute a substantially flat surface.

    摘要翻译: 一种半导体器件,包括形成在第一布线的表面和第一绝缘膜的表面上的基本上平坦的表面上的第二绝缘膜,以覆盖第一布线;形成在第二绝缘膜中的布线沟槽, 在第二绝缘膜上形成的连接孔从布线沟槽延伸到第一布线,形成在第二绝缘膜中的虚拟连接孔从布线沟槽延伸到第一布线的非形成区域,第二布线埋入 在与第一布线电连接并连接在虚拟连接孔中的连接孔和布线沟槽中,并且形成为使得第二布线的表面和第二绝缘膜的表面构成基本平坦的表面。

    Semiconductor device
    2.
    发明申请
    Semiconductor device 有权
    半导体器件

    公开(公告)号:US20050121788A1

    公开(公告)日:2005-06-09

    申请号:US11035745

    申请日:2005-01-18

    摘要: A semiconductor device including a second insulating film formed on a substantially flat surface, on which a surface of a first wiring and a surface of a first insulating film are continued, to cover the first wiring, a wiring trench formed in the second insulating film, connection holes formed in the second insulating film to extend from the wiring trench to the first wiring, dummy connection holes formed in the second insulating film to extend from the wiring trench to a non-forming region of the first wiring, and a second wiring buried in the connection holes and the wiring trench to be connected electrically to the first wiring and also buried in the dummy connection holes, and formed such that a surface of the second wiring and a surface of the second insulating film constitute a substantially flat surface.

    摘要翻译: 一种半导体器件,包括形成在第一布线的表面和第一绝缘膜的表面上的基本上平坦的表面上的第二绝缘膜,以覆盖第一布线;形成在第二绝缘膜中的布线沟槽, 在第二绝缘膜上形成的连接孔从布线沟槽延伸到第一布线,形成在第二绝缘膜中的虚拟连接孔从布线沟槽延伸到第一布线的非形成区域,第二布线埋入 在与第一布线电连接并连接在虚拟连接孔中的连接孔和布线沟槽中,并且形成为使得第二布线的表面和第二绝缘膜的表面构成基本平坦的表面。

    Semiconductor device
    3.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号:US07067919B2

    公开(公告)日:2006-06-27

    申请号:US10309113

    申请日:2002-12-04

    IPC分类号: H01L23/48

    摘要: A semiconductor device including a second insulating film formed on a substantially flat surface, on which a surface of a first wiring and a surface of a first insulating film are continued, to cover the first wiring, a wiring trench formed in the second insulating film, connection holes formed in the second insulating film to extend from the wiring trench to the first wiring, dummy connection holes formed in the second insulating film to extend from the wiring trench to a non-forming region of the first wiring, and a second wiring buried in the connection holes and the wiring trench to be connected electrically to the first wiring and also buried in the dummy connection holes, and formed such that a surface of the second wiring and a surface of the second insulating film constitute a substantially flat surface.

    摘要翻译: 一种半导体器件,包括形成在第一布线的表面和第一绝缘膜的表面上的基本上平坦的表面上的第二绝缘膜,以覆盖第一布线;形成在第二绝缘膜中的布线沟槽, 在第二绝缘膜上形成的连接孔从布线沟槽延伸到第一布线,形成在第二绝缘膜中的虚拟连接孔从布线沟槽延伸到第一布线的非形成区域,第二布线埋入 在与第一布线电连接并连接在虚拟连接孔中的连接孔和布线沟槽中,并且形成为使得第二布线的表面和第二绝缘膜的表面构成基本平坦的表面。

    Semiconductor device
    10.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号:US06750541B2

    公开(公告)日:2004-06-15

    申请号:US10127418

    申请日:2002-04-23

    IPC分类号: H01L2348

    摘要: A semiconductor device having a multi-layered wiring structure containing a copper layer, comprises a first insulating film formed over a semiconductor substrate, a first copper pattern buried in the first insulating film, a cap layer formed on the first copper pattern and the first insulating film and made of a substance a portion of which formed on the first copper pattern has a smaller electrical resistance value than a portion formed on the first insulating film, second insulating films formed on the cap layer, and a second copper pattern buried in a hole or a trench, which is formed in the second insulating films on the first copper pattern, and connected electrically to the first copper pattern via the cap layer.

    摘要翻译: 一种具有包含铜层的多层布线结构的半导体器件,包括形成在半导体衬底上的第一绝缘膜,埋在第一绝缘膜中的第一铜图案,形成在第一铜图案上的帽层和第一绝缘层 由形成在第一铜图案上的部分的物质制成的薄膜比形成在第一绝缘膜上的部分的电阻值小,形成在盖层上的第二绝缘膜和埋在孔中的第二铜图案 或沟槽,其形成在第一铜图案上的第二绝缘膜中,并经由盖层与第一铜图案电连接。