公开(公告)号：US06604229B2

公开(公告)日：2003-08-05

申请号：US09812552

申请日：2001-03-21

申请人： Kenji Suzuki ,  Koji Banno ,  Toru Osajima ,  Takashi Yoneda ,  Takanori Nawa ,  Koji Tsuneto ,  Masuo Inui ,  Hiroyuki Yamamoto

发明人： Kenji Suzuki ,  Koji Banno ,  Toru Osajima ,  Takashi Yoneda ,  Takanori Nawa ,  Koji Tsuneto ,  Masuo Inui ,  Hiroyuki Yamamoto

IPC分类号： G06F1750

CPC分类号： G06F17/5077

摘要： In a higher layer, power source wiring is provisionally provided between a logic-decided functional block and the logic-undecided functional block. Then, a resistor network of the power source wiring within the logic-undecided functional block is prepared by assuming that a current source has been connected to a power source terminal of the logic-undecided functional block. A resistor network of a total power source wiring in the higher layer is prepared by using this local resistor network. An optimum width of the power source wiring is determined by analyzing this resistor network. Based on the width, the power source wiring of the higher layer is rewired.

公开(公告)号：US06496964B2

公开(公告)日：2002-12-17

申请号：US09815053

申请日：2001-03-23

申请人： Masuo Inui ,  Takashi Yoneda ,  Rieko Toki ,  Hiroyuki Yamamoto ,  Kenji Suzuki

发明人： Masuo Inui ,  Takashi Yoneda ,  Rieko Toki ,  Hiroyuki Yamamoto ,  Kenji Suzuki

IPC分类号： G06F945

CPC分类号： G06F17/5045

摘要： A method for designing a semiconductor device having a plurality of logic elements provided with a plurality of power supplies. First, a power supply type name is given to each power supply in accordance with the purpose of the power supply in each logic element. Each logic element is associated with the power supply type name of the power supply that is to be provided to the logic element. A power supply group is formed for each power supply. Specific information of each power supply group associating the power supply type name with supplied voltage is generated. Then, the power supply provided to each logic element is determined by allocating the power supply group to the logic element. The method simplifies designing the layout of a semiconductor device operated by multiple power supplies.

公开(公告)号：US06854094B2

公开(公告)日：2005-02-08

申请号：US10261491

申请日：2002-10-02

申请人： Masuo Inui ,  Takashi Kurihara

发明人： Masuo Inui ,  Takashi Kurihara

IPC分类号： G06F17/50 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04

CPC分类号： G06F17/5077

摘要： A method for designing power supply wiring of a semiconductor integrated circuit having a logic circuit. A first power consumption value of the logic circuit is calculated based on logic connection information, and the power supply wiring is laid out in accordance with the first power consumption value. Logic modification connection information relating to the modified logic circuit is generated when the logic circuit is modified after the power supply wiring is laid out. A second power consumption value of the modified logic circuit is calculated based on the logic modification connection information. When the second power consumption value exceeds the first power consumption value, it is determined that the power supply wiring must be re-laid out. It is thus easily determined whether to re-lay out the power supply wiring without performing power supply network analysis.

摘要翻译： 一种用于设计具有逻辑电路的半导体集成电路的电源布线的方法。 基于逻辑连接信息计算逻辑电路的第一功耗消耗值，并且根据第一功耗值布置电源布线。 在布置电源布线之后，当修改逻辑电路时，产生与修改的逻辑电路相关的逻辑修改连接信息。 基于逻辑修改连接信息计算修改后的逻辑电路的第二功耗值。 当第二功率消耗值超过第一功耗值时，确定必须重新布置电源布线。 因此容易确定是否重新布线电源线，而不进行电源网络分析。