公开(公告)号：US20070136411A1

公开(公告)日：2007-06-14

申请号：US11449794

申请日：2006-06-09

申请人： Toshihiro Katashita ,  Kenji Toda ,  Kazumi Sakamaki ,  Takeshi Inui ,  Tadamasa Takayama ,  Mitsugu Nagoya ,  Yasunori Terashima

发明人： Toshihiro Katashita ,  Kenji Toda ,  Kazumi Sakamaki ,  Takeshi Inui ,  Tadamasa Takayama ,  Mitsugu Nagoya ,  Yasunori Terashima

IPC分类号： G06F7/38

CPC分类号： H03M13/091

摘要： A CRC value calculator enables throughput to be improved while keeping down the increase in the size of the circuitry. This is achieved by using (n+1) basic CRC circuits to configure a CRC value calculator in which the width of the data processed during one clock cycle is m2n bits. For example, when m2n bits is the data width processed per calculator cycle, the CRC value calculator of this invention is configured by using selectors to serially connect a CRC circuit that processes every m2n bits, a CRC circuit that processes every m2(n−1) bits, . . . , and a CRC circuit that processes every m20 bits. This configuration makes it possible to calculate a correct CRC value even when the remainder of an input network frame is not a multiple of m2n bits. Selectors are used to select CRC circuit output according to process data width. Reduction of the operating frequency is avoided by using registers to form a pipeline between CRC circuits.

摘要翻译： CRC值计算器能够提高吞吐量，同时降低电路尺寸的增加。 这通过使用（n + 1）个基本CRC电路来配置CRC值计算器来实现，其中在一个时钟周期期间处理的数据的宽度是m2 比特。 例如，当每个计算器周期处理数据宽度为m2时，本发明的CRC值计算器通过使用选择器来串行连接CRC电路来配置，该CRC电路处理每个m2 < / SUP>位，每个m2（n-1）位处理的CRC电路。 。 。 以及处理每个m2 <0>比特的CRC电路。 该配置使得即使当输入网络帧的剩余部分不是m2 比特的倍数时，也可以计算正确的CRC值。 选择器用于根据过程数据宽度选择CRC电路输出。 通过使用寄存器在CRC电路之间形成流水线来避免工作频率的降低。

公开(公告)号：US07953014B2

公开(公告)日：2011-05-31

申请号：US11368415

申请日：2006-03-07

申请人： Kenji Toda ,  Toshihiro Katashita ,  Kazumi Sakamaki ,  Takeshi Inui ,  Mitsugu Nagoya ,  Yasunori Terashima

发明人： Kenji Toda ,  Toshihiro Katashita ,  Kazumi Sakamaki ,  Takeshi Inui ,  Mitsugu Nagoya ,  Yasunori Terashima

IPC分类号： H04L12/26 ,  G01R31/08 ,  G06F11/00 ,  G06F7/04 ,  H04L29/08

CPC分类号： H04L43/50

摘要： Network device testing equipment capable of testing network devices using small size packets and for a transferring ability and a filtering ability at a media speed is described. A configuration is adopted in which a Field Programmable Gate Array (FPGA) included in a transmitter or receiver on one or both of transmitting and receiving sides is connected directly to a physical layer chip of a network and computers on both the transmitting and receiving sides are connected thereto. Each of the FPGAs of the transmitter and receiver has a circuit which has an integrated function of transmitting a packet pattern generation function and a packet-receiving function, thereby enabling a test and an inspection in real time. When inspecting the filtering function, a hash table storing therein a hash value and a list of occurrence frequencies for hash values is utilized. In order to avoid the hash values of different packets from having a same value, the hash function is configured so as to avoid that the same hash value is given to different packets or, when packet values have a common hash value, the packet is re-shaped into a packet having a different hash value.

摘要翻译： 描述了能够使用小尺寸数据包测试网络设备的网络设备测试设备以及媒体速度下的传送能力和过滤能力。 采用这样的配置，其中包括在发射机和接收机中的一个或两个的发射机或接收机中的现场可编程门阵列（FPGA）直接连接到网络的物理层芯片，并且发射和接收侧的计算机 与其连接。 发送器和接收器的每个FPGA具有具有发送分组模式生成功能和分组接收功能的集成功能的电路，从而实现测试和检查。 当检查过滤功能时，利用其中存储散列值的散列表和散列值的出现频率列表。 为了避免不同分组的哈希值具有相同的值，散列函数被配置为避免向不同的分组赋予相同的哈希值，或者当分组值具有公共散列值时，分组是re 形成具有不同哈希值的分组。

公开(公告)号：US07590916B2

公开(公告)日：2009-09-15

申请号：US11449794

申请日：2006-06-09

申请人： Toshihiro Katashita ,  Kenji Toda ,  Kazumi Sakamaki ,  Takeshi Inui ,  Tadamasa Takayama ,  Mitsugu Nagoya ,  Yasunori Terashima

发明人： Toshihiro Katashita ,  Kenji Toda ,  Kazumi Sakamaki ,  Takeshi Inui ,  Tadamasa Takayama ,  Mitsugu Nagoya ,  Yasunori Terashima

IPC分类号： H03M13/09

CPC分类号： H03M13/091

摘要： A CRC value calculator enables throughput to be improved while keeping down the increase in the size of the circuitry. This is achieved by using (n+1) basic CRC circuits to configure a CRC value calculator in which the width of the data processed during one clock cycle is m2n bits. For example, when m2n bits is the data width processed per calculator cycle, the CRC value calculator of this invention is configured by using selectors to serially connect a CRC circuit that processes every m2n bits, a CRC circuit that processes every m2(n−1) bits, . . . , and a CRC circuit that processes every m20 bits. This configuration makes it possible to calculate a correct CRC value even when the remainder of an input network frame is not a multiple of m2n bits. Selectors are used to select CRC circuit output according to process data width. Reduction of the operating frequency is avoided by using registers to form a pipeline between CRC circuits.

摘要翻译： CRC值计算器能够提高吞吐量，同时降低电路尺寸的增加。 这通过使用（n + 1）个基本CRC电路来配置CRC值计算器来实现，其中在一个时钟周期期间处理的数据的宽度是m2n位。 例如，当m2n位是每个计算周期处理的数据宽度时，本发明的CRC值计算器通过使用选择器来串行连接处理每m2n位的CRC电路，每个m2（n-1）处理的CRC电路 ）位。 。 。 ，以及处理每m20位的CRC电路。 该配置使得即使当输入网络帧的剩余部分不是m2n位的倍数时，也可以计算正确的CRC值。 选择器用于根据过程数据宽度选择CRC电路输出。 通过使用寄存器在CRC电路之间形成流水线来避免工作频率的降低。

公开(公告)号：US20070067130A1

公开(公告)日：2007-03-22

申请号：US11368415

申请日：2006-03-07

申请人： Kenji Toda ,  Toshihiro Katashita ,  Kazumi Sakamaki ,  Takeshi Inui ,  Mitsugu Nagoya ,  Yasunori Terashima

发明人： Kenji Toda ,  Toshihiro Katashita ,  Kazumi Sakamaki ,  Takeshi Inui ,  Mitsugu Nagoya ,  Yasunori Terashima

IPC分类号： G06F19/00

CPC分类号： H04L43/50

摘要： Network device testing equipment capable of testing network devices using small size packets and for a transferring ability and a filtering ability at a media speed is described. A configuration is adopted in which a Field Programmable Gate Array (FPGA) included in a transmitter or receiver on one or both of transmitting and receiving sides is connected directly to a physical layer chip of a network and computers on both the transmitting and receiving sides are connected thereto. Each of the FPGAs of the transmitter and receiver has a circuit which has an integrated function of transmitting a packet pattern generation function and a packet-receiving function, thereby enabling a test and an inspection in real time. When inspecting the filtering function, a hash table storing therein a hash value and a list of occurrence frequencies for hash values is utilized. In order to avoid the hash values of different packets from having a same value, the hash function is configured so as to avoid that the same hash value is given to different packets or, when packet values have a common hash value, the packet is re-shaped into a packet having a different hash value.

摘要翻译： 描述了能够使用小尺寸数据包测试网络设备的网络设备测试设备以及媒体速度下的传送能力和过滤能力。 采用这样的配置，其中包括在发射机和接收机中的一个或两个的发射机或接收机中的现场可编程门阵列（FPGA）直接连接到网络的物理层芯片，并且发射和接收侧的计算机 与其连接。 发送器和接收器的每个FPGA具有具有发送分组模式生成功能和分组接收功能的集成功能的电路，从而实现测试和检查。 当检查过滤功能时，利用其中存储散列值的散列表和散列值的出现频率列表。 为了避免不同分组的哈希值具有相同的值，散列函数被配置为避免向不同的分组赋予相同的哈希值，或者当分组值具有公共散列值时，分组是re 形成具有不同哈希值的分组。

公开(公告)号：US07843401B2

公开(公告)日：2010-11-30

申请号：US11526630

申请日：2006-09-26

申请人： Osamu Morikawa ,  Kenji Toda ,  Toshihiro Katashita ,  Yohei Hori

发明人： Osamu Morikawa ,  Kenji Toda ,  Toshihiro Katashita ,  Yohei Hori

IPC分类号： G09G5/00

CPC分类号： G06F3/1446 ,  G09G2340/0464 ,  G09G2370/04 ,  H04N9/12

摘要： An image display apparatus for displaying image signals of a form of packets incorporating display position information includes a combination of unit display devices so as to acquire translational objectivity. Each of the unit display devices including a receiving part for receiving image signals, a processing part for dividing input image signals into those falling inside and those falling outside a range for display or those subject to or those not subject to display based on the display position information and serving to process display positions of the image signals falling outside the range for display or not subject to display, an output part for outputting the processed image signals along an axis of translational objectivity to a subsequent unit display device, and a display part for displaying the images falling in the range for display, the image display apparatus displaying the image signals as a whole, with the image signals processed sequentially with the unit display devices.

摘要翻译： 用于显示包含显示位置信息的分组形式的图像信号的图像显示装置包括单元显示装置的组合，以获得平移客观性。 每个单元显示装置包括用于接收图像信号的接收部分，用于将输入图像信号分为内部的输入图像信号的处理部分和落在用于显示的范围之外的处理部分，或者基于显示位置的不受显示的那些 信息和服务以处理落在用于显示或不显示的范围之外的图像信号的显示位置，用于将经处理的图像信号沿着平移客观性的轴输出到后续单元显示装置的输出部分，以及用于 显示落在显示范围内的图像，图像显示装置整体地显示图像信号，图像信号与单元显示装置顺序处理。

公开(公告)号：US20070285342A1

公开(公告)日：2007-12-13

申请号：US11526630

申请日：2006-09-26

申请人： Osamu Morikawa ,  Kenji Toda ,  Toshihiro Katashita ,  Yohei Hori

发明人： Osamu Morikawa ,  Kenji Toda ,  Toshihiro Katashita ,  Yohei Hori

IPC分类号： G09G5/00

CPC分类号： G06F3/1446 ,  G09G2340/0464 ,  G09G2370/04 ,  H04N9/12

摘要： An image display apparatus for displaying image signals of a form of packets incorporating display position information includes a combination of unit display devices so as to acquire translational objectivity. Each of the unit display devices including a receiving part for receiving image signals, a processing part for dividing input image signals into those falling inside and those falling outside a range for display or those subject to or those not subject to display based on the display position information and serving to process display positions of the image signals falling outside the range for display or not subject to display, an output part for outputting the processed image signals along an axis of translational objectivity to a subsequent unit display device, and a display part for displaying the images falling in the range for display, the image display apparatus displaying the image signals as a whole, with the image signals processed sequentially with the unit display devices.

摘要翻译： 用于显示包含显示位置信息的分组形式的图像信号的图像显示装置包括单元显示装置的组合，以获得平移客观性。 每个单元显示装置包括用于接收图像信号的接收部分，用于将输入图像信号分为内部的输入图像信号的处理部分和落在用于显示的范围之外的处理部分，或者基于显示位置的不受显示的那些 信息和服务以处理落在用于显示或不显示的范围之外的图像信号的显示位置，用于将经处理的图像信号沿着平移客观性的轴输出到后续单元显示装置的输出部分，以及用于 显示落在显示范围内的图像，图像显示装置整体地显示图像信号，图像信号与单元显示装置顺序处理。

公开(公告)号：US20090085009A1

公开(公告)日：2009-04-02

申请号：US11575386

申请日：2006-04-04

申请人： Kenji Toda ,  Mineo Sato ,  Kazuyoshi Uematsu ,  Shinichiro Kousaka ,  Yoshitaka Kawakami

发明人： Kenji Toda ,  Mineo Sato ,  Kazuyoshi Uematsu ,  Shinichiro Kousaka ,  Yoshitaka Kawakami

IPC分类号： C09K11/59

CPC分类号： H05B33/14 ,  C09K11/7734 ,  C09K11/7774 ,  H01L33/502

摘要： A novel fluorescent substance for a light-emitting diode, emitting light of any one of three primary colors by excitation of an ultraviolet light-emitting diode. Alternatively, a novel fluorescent substance for a light-emitting diode, emitting light in a red region of a spectrum by excitation of a blue light-emitting diode. Na2SrSi2O6 is doped with Eu3+. Preferably, Eu3+ is added so as to account for 1 to 80 mol % in concentration in a host crystal, while sites of Si4+ in Na2SrSi2O6. are replaced by Al3+ and/or Ga3+. Alternatively, Ca3Si2O7 is doped with Ce3+ and Tb3+. Preferably, Ce3+ and Tb3+ are added so as to account for 0.1 to 80 mol % and 0.1 to 20 mol % in concentration in a host crystal, respectively. Still alternatively, Ca3Si2O7 is doped with Eu2+. Preferably, Eu2+ is added so as to account for 0.5 to 10 mol % in concentration in the host crystal.

摘要翻译： 一种用于发光二极管的新型荧光物质，通过激发紫外发光二极管发射三原色中的任一种的光。 或者，用于发光二极管的新型荧光物质，通过蓝色发光二极管的激发在光谱的红色区域中发光。 Na2SrSi2O6掺杂Eu3 +。 优选添加Eu 3+，以使主体晶体中的浓度为1〜80摩尔％，而Na 2 S 6 Si 2 O 6中的Si 4+的位置。 被Al3 +和/或Ga3 +代替。 或者，Ca 3 Si 2 O 7掺杂有Ce 3+和Tb 3+。 优选分别加入Ce3 +和Tb3 +，使其在主晶体中的浓度分别为0.1〜80mol％和0.1〜20mol％。 或者，Ca 3 Si 2 O 7掺杂有Eu 2+。 优选加入Eu 2+以使其在主晶体中的浓度为0.5〜10摩尔％。

公开(公告)号：US20050016961A1

公开(公告)日：2005-01-27

申请号：US10896465

申请日：2004-07-22

申请人： Kenji Toda ,  Yukari Morinaga ,  Takahiro Teshima ,  Ai Kuroda

发明人： Kenji Toda ,  Yukari Morinaga ,  Takahiro Teshima ,  Ai Kuroda

IPC分类号： C23F1/18 ,  H05K3/06 ,  C23F1/00

CPC分类号： C23F1/18 ,  H05K3/067 ,  H05K2203/124

摘要： An etchant for copper and copper alloys, includes an aqueous solution containing: 14 to 155 g/liter of cupric ion source in terms of a concentration of copper ions; 7 to 180 g/liter of hydrochloric acid; and 0.1 to 50 g/liter of azole, the azole including nitrogen atoms only as heteroatoms residing in a ring. A method for producing a wiring by etching of copper or copper alloys, includes the step of: etching a portion of a copper layer on an electrical insulative member that is not covered with an etching resist using the above-described etchant so as to form the wiring. Thereby, a fine and dense wiring pattern with reduced undercut can be formed.

摘要翻译： 铜和铜合金的蚀刻剂包括含有以铜离子浓度计的14至155g /升铜离子源的水溶液; 7〜180g / l盐酸; 和0.1至50g / l的唑，唑类仅包括驻留在环中的杂原子的氮原子。 通过蚀刻铜或铜合金制造布线的方法包括以下步骤：使用上述蚀刻剂蚀刻未被抗蚀剂覆盖的电绝缘构件上的铜层的一部分，以形成 接线。 由此，可以形成具有减小的底切的精密且致密的布线图案。

公开(公告)号：US06627112B2

公开(公告)日：2003-09-30

申请号：US09730581

申请日：2000-12-07

申请人： Kenji Toda ,  Keiji Ono ,  Susumu Miyazaki

发明人： Kenji Toda ,  Keiji Ono ,  Susumu Miyazaki

IPC分类号： H01J1102

CPC分类号： C09K11/7774 ,  C09K11/774 ,  C09K11/7769 ,  C09K11/7775 ,  C09K11/7787 ,  C09K11/7792 ,  C09K11/7793

摘要： A phosphor for a vacuum ultraviolet excited light emitting device, obtained (1) by adding Eu or Tb as an activating agent to a substrate comprising a compound represented by the general formula M1M2M3O4, wherein M1 represents at least one element selected from Na and Li, M2 represents at least one element selected from Gd and Y, and M3 at least one element selected from Ge and Si; (2) by adding Eu as an activating agent to a substrate comprising a compound containing SrO, Al2O3 and B2O3; or (3) by adding Eu or Tb as an activating agent to a substrate comprising a compound represented by the general formula M2O2CN2, wherein M represents at least one element selected from La, Y and Gd.

摘要翻译： 一种用于真空紫外激发发光器件的荧光体，其通过将Eu或Tb作为活化剂添加到包含由通式M 1 M 2 M 3 O 4表示的化合物的基材中而获得（其中， M 1表示选自Na和Li中的至少一种元素，M 2表示选自Gd和Y中的至少一种元素，M 3选自Ge和Si中的至少一种元素; （2）通过将Eu作为活化剂添加到包含含有SrO，Al 2 O 3和B 2 O 3的化合物的基材中; 或（3）通过将Eu或Tb作为活化剂添加到包含由通式M 2 O 2 CN 2表示的化合物的基材中，其中M表示选自La，Y和Gd中的至少一种元素。

公开(公告)号：US08429749B2

公开(公告)日：2013-04-23

申请号：US12055651

申请日：2008-03-26

申请人： Eiichi Takahashi ,  Masahiro Yasuda ,  Yosuke Iijima ,  Masahiro Murakawa ,  Kenji Toda ,  Tetsuya Higuchi

发明人： Eiichi Takahashi ,  Masahiro Yasuda ,  Yosuke Iijima ,  Masahiro Murakawa ,  Kenji Toda ,  Tetsuya Higuchi

IPC分类号： H04L29/06

CPC分类号： H04L63/145 ,  G06F21/562 ,  G06F21/57

摘要： A network system by the present invention can quickly detect viruses and does not easily become a new cause of vulnerability. A packet data comparator branches inputted packet data into three branches, and includes an additional pattern matching unit which compares the branched data with the stored data and performs matching with collation patterns stored in a rewritable storage area, a fixed pattern matching unit which compares the branched data with the stored data and performs the matching with a logical operation configured with known collation patterns, a notification packet matching unit which compares the branched data with the stored data and finds a notification packet, and an identity detection aggregation unit which aggregates results from the respective matching units. Moreover, a virus filter, a virus checker, and a secure network system are realized by using the present invention.

摘要翻译： 本发明的网络系统可以快速检测病毒，不容易成为新的漏洞。 分组数据比较器将输入的分组数据分成三个分支，并且包括附加模式匹配单元，其将分支数据与存储的数据进行比较，并且与存储在可重写存储区域中的对照模式进行匹配，固定模式匹配单元， 数据与存储的数据进行匹配，并且执行与已知对照模式配置的逻辑操作的匹配;通知分组匹配单元，其将分支数据与所存储的数据进行比较并找到通知分组;以及身份检测聚合单元， 各匹配单位。 此外，通过使用本发明来实现病毒过滤器，病毒检查器和安全网络系统。