公开(公告)号：US07953014B2

公开(公告)日：2011-05-31

申请号：US11368415

申请日：2006-03-07

申请人： Kenji Toda ,  Toshihiro Katashita ,  Kazumi Sakamaki ,  Takeshi Inui ,  Mitsugu Nagoya ,  Yasunori Terashima

发明人： Kenji Toda ,  Toshihiro Katashita ,  Kazumi Sakamaki ,  Takeshi Inui ,  Mitsugu Nagoya ,  Yasunori Terashima

IPC分类号： H04L12/26 ,  G01R31/08 ,  G06F11/00 ,  G06F7/04 ,  H04L29/08

CPC分类号： H04L43/50

摘要： Network device testing equipment capable of testing network devices using small size packets and for a transferring ability and a filtering ability at a media speed is described. A configuration is adopted in which a Field Programmable Gate Array (FPGA) included in a transmitter or receiver on one or both of transmitting and receiving sides is connected directly to a physical layer chip of a network and computers on both the transmitting and receiving sides are connected thereto. Each of the FPGAs of the transmitter and receiver has a circuit which has an integrated function of transmitting a packet pattern generation function and a packet-receiving function, thereby enabling a test and an inspection in real time. When inspecting the filtering function, a hash table storing therein a hash value and a list of occurrence frequencies for hash values is utilized. In order to avoid the hash values of different packets from having a same value, the hash function is configured so as to avoid that the same hash value is given to different packets or, when packet values have a common hash value, the packet is re-shaped into a packet having a different hash value.

摘要翻译： 描述了能够使用小尺寸数据包测试网络设备的网络设备测试设备以及媒体速度下的传送能力和过滤能力。 采用这样的配置，其中包括在发射机和接收机中的一个或两个的发射机或接收机中的现场可编程门阵列（FPGA）直接连接到网络的物理层芯片，并且发射和接收侧的计算机 与其连接。 发送器和接收器的每个FPGA具有具有发送分组模式生成功能和分组接收功能的集成功能的电路，从而实现测试和检查。 当检查过滤功能时，利用其中存储散列值的散列表和散列值的出现频率列表。 为了避免不同分组的哈希值具有相同的值，散列函数被配置为避免向不同的分组赋予相同的哈希值，或者当分组值具有公共散列值时，分组是re 形成具有不同哈希值的分组。

公开(公告)号：US07590916B2

公开(公告)日：2009-09-15

申请号：US11449794

申请日：2006-06-09

申请人： Toshihiro Katashita ,  Kenji Toda ,  Kazumi Sakamaki ,  Takeshi Inui ,  Tadamasa Takayama ,  Mitsugu Nagoya ,  Yasunori Terashima

发明人： Toshihiro Katashita ,  Kenji Toda ,  Kazumi Sakamaki ,  Takeshi Inui ,  Tadamasa Takayama ,  Mitsugu Nagoya ,  Yasunori Terashima

IPC分类号： H03M13/09

CPC分类号： H03M13/091

摘要： A CRC value calculator enables throughput to be improved while keeping down the increase in the size of the circuitry. This is achieved by using (n+1) basic CRC circuits to configure a CRC value calculator in which the width of the data processed during one clock cycle is m2n bits. For example, when m2n bits is the data width processed per calculator cycle, the CRC value calculator of this invention is configured by using selectors to serially connect a CRC circuit that processes every m2n bits, a CRC circuit that processes every m2(n−1) bits, . . . , and a CRC circuit that processes every m20 bits. This configuration makes it possible to calculate a correct CRC value even when the remainder of an input network frame is not a multiple of m2n bits. Selectors are used to select CRC circuit output according to process data width. Reduction of the operating frequency is avoided by using registers to form a pipeline between CRC circuits.

摘要翻译： CRC值计算器能够提高吞吐量，同时降低电路尺寸的增加。 这通过使用（n + 1）个基本CRC电路来配置CRC值计算器来实现，其中在一个时钟周期期间处理的数据的宽度是m2n位。 例如，当m2n位是每个计算周期处理的数据宽度时，本发明的CRC值计算器通过使用选择器来串行连接处理每m2n位的CRC电路，每个m2（n-1）处理的CRC电路 ）位。 。 。 ，以及处理每m20位的CRC电路。 该配置使得即使当输入网络帧的剩余部分不是m2n位的倍数时，也可以计算正确的CRC值。 选择器用于根据过程数据宽度选择CRC电路输出。 通过使用寄存器在CRC电路之间形成流水线来避免工作频率的降低。

公开(公告)号：US20070067130A1

公开(公告)日：2007-03-22

申请号：US11368415

申请日：2006-03-07

申请人： Kenji Toda ,  Toshihiro Katashita ,  Kazumi Sakamaki ,  Takeshi Inui ,  Mitsugu Nagoya ,  Yasunori Terashima

发明人： Kenji Toda ,  Toshihiro Katashita ,  Kazumi Sakamaki ,  Takeshi Inui ,  Mitsugu Nagoya ,  Yasunori Terashima

IPC分类号： G06F19/00

CPC分类号： H04L43/50

摘要： Network device testing equipment capable of testing network devices using small size packets and for a transferring ability and a filtering ability at a media speed is described. A configuration is adopted in which a Field Programmable Gate Array (FPGA) included in a transmitter or receiver on one or both of transmitting and receiving sides is connected directly to a physical layer chip of a network and computers on both the transmitting and receiving sides are connected thereto. Each of the FPGAs of the transmitter and receiver has a circuit which has an integrated function of transmitting a packet pattern generation function and a packet-receiving function, thereby enabling a test and an inspection in real time. When inspecting the filtering function, a hash table storing therein a hash value and a list of occurrence frequencies for hash values is utilized. In order to avoid the hash values of different packets from having a same value, the hash function is configured so as to avoid that the same hash value is given to different packets or, when packet values have a common hash value, the packet is re-shaped into a packet having a different hash value.

摘要翻译： 描述了能够使用小尺寸数据包测试网络设备的网络设备测试设备以及媒体速度下的传送能力和过滤能力。 采用这样的配置，其中包括在发射机和接收机中的一个或两个的发射机或接收机中的现场可编程门阵列（FPGA）直接连接到网络的物理层芯片，并且发射和接收侧的计算机 与其连接。 发送器和接收器的每个FPGA具有具有发送分组模式生成功能和分组接收功能的集成功能的电路，从而实现测试和检查。 当检查过滤功能时，利用其中存储散列值的散列表和散列值的出现频率列表。 为了避免不同分组的哈希值具有相同的值，散列函数被配置为避免向不同的分组赋予相同的哈希值，或者当分组值具有公共散列值时，分组是re 形成具有不同哈希值的分组。

公开(公告)号：US06243665B1

公开(公告)日：2001-06-05

申请号：US08894630

申请日：1997-08-22

申请人： Mitsugu Nagoya ,  Kazumi Sakamaki

发明人： Mitsugu Nagoya ,  Kazumi Sakamaki

IPC分类号： G06F944

CPC分类号： G06F11/0796 ,  G01R31/31728 ,  G01R31/318511 ,  G01R31/318544 ,  G01R31/31855 ,  G01R31/318555 ,  G06F11/22 ,  G06F11/327

摘要： The monitoring control apparatus according to the present invention performs a test on each integrated circuit that supports the boundary scan test method loaded on CPU board 4 and control board 5, and on the connection relationships of these integrated circuits, by a boundary scan controller board 7 like that shown, for example, in FIG. 1. If an abnormality is detected in CPU board 4 or control board 5, an alarm apparatus 9 is activated which emits an alarm. Moreover, if the type of abnormality is such that there is the risk of it having a significant effect on the operation of a robot 3, which is the target of this monitoring and control, from the viewpoint of safety, main power supply apparatus 6 of robot 3 is interrupted to prevent in advance robot 3 from running out of control.

摘要翻译： 根据本发明的监视控制装置对支持CPU板4和控制板5上的边界扫描测试方法的每个集成电路进行测试，并且通过边界扫描控制器板7对这些集成电路的连接关系进行测试 如图所示， 1.如果在CPU板4或控制板5中检测到异常，则启动报警装置9，发出报警。 此外，从安全性的观点来看，如果异常的种类存在对作为该监视和控制的对象的机器人3的操作具有显着影响的风险，则从安全性的观点出发，主电源装置6 机器人3被中断以防止事先机器人3失去控制。

公开(公告)号：US20070136411A1

公开(公告)日：2007-06-14

申请号：US11449794

申请日：2006-06-09

申请人： Toshihiro Katashita ,  Kenji Toda ,  Kazumi Sakamaki ,  Takeshi Inui ,  Tadamasa Takayama ,  Mitsugu Nagoya ,  Yasunori Terashima

发明人： Toshihiro Katashita ,  Kenji Toda ,  Kazumi Sakamaki ,  Takeshi Inui ,  Tadamasa Takayama ,  Mitsugu Nagoya ,  Yasunori Terashima

IPC分类号： G06F7/38

CPC分类号： H03M13/091

摘要： A CRC value calculator enables throughput to be improved while keeping down the increase in the size of the circuitry. This is achieved by using (n+1) basic CRC circuits to configure a CRC value calculator in which the width of the data processed during one clock cycle is m2n bits. For example, when m2n bits is the data width processed per calculator cycle, the CRC value calculator of this invention is configured by using selectors to serially connect a CRC circuit that processes every m2n bits, a CRC circuit that processes every m2(n−1) bits, . . . , and a CRC circuit that processes every m20 bits. This configuration makes it possible to calculate a correct CRC value even when the remainder of an input network frame is not a multiple of m2n bits. Selectors are used to select CRC circuit output according to process data width. Reduction of the operating frequency is avoided by using registers to form a pipeline between CRC circuits.

摘要翻译： CRC值计算器能够提高吞吐量，同时降低电路尺寸的增加。 这通过使用（n + 1）个基本CRC电路来配置CRC值计算器来实现，其中在一个时钟周期期间处理的数据的宽度是m2 比特。 例如，当每个计算器周期处理数据宽度为m2时，本发明的CRC值计算器通过使用选择器来串行连接CRC电路来配置，该CRC电路处理每个m2 < / SUP>位，每个m2（n-1）位处理的CRC电路。 。 。 以及处理每个m2 <0>比特的CRC电路。 该配置使得即使当输入网络帧的剩余部分不是m2 比特的倍数时，也可以计算正确的CRC值。 选择器用于根据过程数据宽度选择CRC电路输出。 通过使用寄存器在CRC电路之间形成流水线来避免工作频率的降低。