公开(公告)号：US11832451B1

公开(公告)日：2023-11-28

申请号：US17396609

申请日：2021-08-06

Applicant: Kepler Computing Inc.

Inventor： Debraj Guhabiswas ,  Maria Isabel Perez ,  Jason Y. Wu ,  James David Clarkson ,  Gabriel Antonio Paulius Velarde ,  Niloy Mukherjee ,  Noriyuki Sato ,  Amrita Mathuriya ,  Sasikanth Manipatruni ,  Ramamoorthy Ramesh

IPC: H01L21/00 ,  H10B53/30 ,  H01L49/02

CPC classification number: H10B53/30 ,  H01L28/55 ,  H01L28/60

Abstract: Non lead-based perovskite ferroelectric devices for high density memory and logic applications and methods of fabrication are described. While various embodiments are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For example, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.

公开(公告)号：US12108607B1

公开(公告)日：2024-10-01

申请号：US17502942

申请日：2021-10-15

Applicant: Kepler Computing Inc.

Inventor： Noriyuki Sato ,  Debraj Guhabiswas ,  Tanay Gosavi ,  Niloy Mukherjee ,  Amrita Mathuriya ,  Sasikanth Manipatruni

IPC: H10B53/30 ,  H01L49/02 ,  H10B53/40

CPC classification number: H10B53/30 ,  H01L28/60 ,  H10B53/40

Abstract: An integration process including an etch stop layer for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.

公开(公告)号：US12108608B1

公开(公告)日：2024-10-01

申请号：US17503009

申请日：2021-10-15

Applicant: Kepler Computing Inc.

Inventor： Noriyuki Sato ,  Debraj Guhabiswas ,  Tanay Gosavi ,  Niloy Mukherjee ,  Amrita Mathuriya ,  Sasikanth Manipatruni

IPC: H10B53/30 ,  H01L49/02

CPC classification number: H10B53/30 ,  H01L28/60

Abstract: An integration process including an etch stop layer for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.