公开(公告)号：US20090261869A1

公开(公告)日：2009-10-22

申请号：US12104246

申请日：2008-04-16

申请人： Kevin GILLESPIE ,  Guhan KRISHNAN ,  Maurice STEINMAN ,  Spencer GOLD ,  Bill K.C. KWAN

发明人： Kevin GILLESPIE ,  Guhan KRISHNAN ,  Maurice STEINMAN ,  Spencer GOLD ,  Bill K.C. KWAN

IPC分类号： H03L7/00

CPC分类号： G06F1/12

摘要： Two clock domains of a data processing device are each synchronized with a different clock signal. The clock signals are generated by clock generation logic. The clock generation logic also generates a transfer enable signal based on the relative frequency of each clock signal to indicate when data can be transferred between the clock domains. Further, as the relative frequency of the clock signals change, the timing of the transfer enable signal also changes to ensure reliable data transfer.

摘要翻译： 数据处理装置的两个时钟域各自与不同的时钟信号同步。 时钟信号由时钟产生逻辑产生。 时钟生成逻辑还基于每个时钟信号的相对频率产生传输使能信号，以指示何时可以在时钟域之间传送数据。 此外，随着时钟信号的相对频率变化，传送使能信号的定时也改变，以确保可靠的数据传输。