公开(公告)号：US06728914B2

公开(公告)日：2004-04-27

申请号：US09745603

申请日：2000-12-22

申请人： Kevin William McCauley ,  William Vincent Huott ,  Mary Prilotski Kusko ,  Peilin Song ,  Richard Frank Rizzolo ,  Ulrich Baur ,  Franco Motika

发明人： Kevin William McCauley ,  William Vincent Huott ,  Mary Prilotski Kusko ,  Peilin Song ,  Richard Frank Rizzolo ,  Ulrich Baur ,  Franco Motika

IPC分类号： G01R3128

CPC分类号： G01R31/318385 ,  G01R31/31858

摘要： For each logic gate in a logic circuit, all paths containing the gate are determined and the paths are classified by their length between each of the input or launch SRLs and each output or capture SRL. The paths are assigned a single threshold value and then divided into two groups in accordance with their path length classification relative to the threshold value with all paths in each group treated as a single path. Pseudo random LBIST patterns are then simulated using standard LBIST tool. When a fault associated with a logic gate is detected by a capture SRL of a path with a length above the threshold, the fault is viewed as tested and marked off from the fault list. When a fault is detected in any path that is below the threshold, it is not marked off and testing of the fault continues until testing patterns for all the paths of the group falling below the threshold value are simulated. When all the faults paths of the group falling below the threshold have been tested, a separate determined test generation program is activated. In the generated test, the fault is forced to propagate through the longest path above the threshold value.

摘要翻译： 对于逻辑电路中的每个逻辑门，确定包含门的所有路径，并且通过其每个输入或启动SRL和每个输出或捕获SRL之间的长度对路径进行分类。 路径被分配单个阈值，然后根据它们相对于阈值的路径长度分类被分成两组，每组中的所有路径被视为单个路径。 然后使用标准LBIST工具模拟伪随机LBIST图案。 当与逻辑门相关联的故障由长度高于阈值的路径的捕获​​SRL检测到时，故障被视为测试并从故障列表中标记出来。 当在低于阈值的任何路径中检测到故障时，它不会被标记，并且故障的测试继续进行，直到测试模式为低于阈值的组的所有路径。 当组件的所有故障路径都低于阈值时，已经测试了单独确定的测试生成程序。 在生成的测试中，故障被迫通过超过阈值的最长路径传播。