公开(公告)号：US20250080447A1

公开(公告)日：2025-03-06

申请号：US18386245

申请日：2023-11-01

Applicant: Keysight Technologies, Inc.

Inventor： Pinaki Chakrabarti

IPC: H04L43/50 ,  H04L43/106

Abstract: One example method occurs at a test system implemented using at least one processor. The method includes receiving test configuration information associated with a test session for causing one or more packets to be transmitted via lanes connecting a transmitter and a receiver in a test environment; transmitting, from the transmitter and to the receiver, a first packet of the test session, wherein transmitting the first packet as data blocks and sending the data blocks via the lanes, wherein transmitting the first packet includes emulating lane skewing associated with one or more of the lanes causing at least some of the data blocks to arrive at different times; receiving a first ingress timestamp associated with the first packet; and analyzing the first ingress timestamp and a first expected ingress timestamp based on lane skew information associated with the test session.

公开(公告)号：US20250119270A1

公开(公告)日：2025-04-10

申请号：US18378113

申请日：2023-10-09

Applicant: Keysight Technologies, Inc.

Inventor： Noah Steven Gintis ,  Pinaki Chakrabarti

IPC: H04L7/02 ,  H04J3/06

Abstract: A method for correlating and displaying physical layer and application layer timing information includes detecting an edge transition of a physical layer waveform from a physical clock on a DUT and generating a timestamp for the detected edge transition. A physical clock timing error is determined based on the timestamp for the detected edge transition. Timing protocol messages are exchanged between the test system and the DUT. The test system generates timestamps when transmitting or receiving the timing protocol messages and receives timestamp information from the DUT and a protocol time is determined. The physical clock timing error and the protocol time are correlated and relative times of the physical clock timing error and the protocol time are determined. The method further includes displaying, by a graphical user interface on the test system, a graphical representation of the relative times of the physical clock timing error and the protocol time.